271hw5 sol - Assignments PDF

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SAN JOSE STATE UNIVERSITY College of Engineering

DEPARTMENT OF ELECTRICAL ENGINEERING EE271

Homework #5 Solution 1. An addition circuit running at 100MHz with a supply voltage of 3V. Assume that on the average each node change states (from 0 to 1 or from 1 to 0) 2 times per 10 clock cycles and the total internal node capacitance is 10fF. Find the power consumption in the adder. Solution Straight-forward using the formula # gates

2 Pdynamic ≈ 0.5Vdd f clock ∑ ⎣⎡riC Li ⎦⎤ i =1

(

)

(

= 0.5 × (3 ) × 100 × 10 6 × 0.20 × 10 × 10 −15 2

= 0.9 × 10

−6

= 0.9 μW10

)

−15

2. Modify the Verilog code below to improve the power consumption. Assume that signal enable is active (high) 20% of the time. Assume the adder consumes too little power that it is not worth to consider it for power optimization. reg Enable; reg [31:0] A, B, DataOut, MultOut, AddOut; wire [31:0] A, B; always@(posedge clock) if (Enable == 1) DataOut...