8086 & Instruction Pipelining PDF

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Notes on 8086 & Instruction Pipelining and Pile Hazards...

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8086 It's a 16-bit microprocessor with 20 address lines and 16 data lines, and it can store up to 1MB of data. It has a robust instruction set that makes operations like multiplication and division simple. Figure 1 shows the architecture of the 8086 processor. It consists of two distinct functional units— 

Bus Interface Unit (BIU) and



Execution Unit (EU).

Figure 1

Instruction Pipelining Greater performance can be achieved when computer systems grow by utilizing technological advancements such as quicker circuitry. In addition, improvements to the processor's structure can help it operate better. Some examples are the use of many registers instead of a single accumulator and the usage of cache memory. Instruction pipelining is another typical organizational strategy.

Pipelining Strategy  The usage of an assembly line in a manufacturing facility is analogous to instruction pipelining. An assembly line takes use of the fact that a product passes through several stages of manufacturing.  Products at various stages can be worked on concurrently by putting up the production process in an assembly line. Because fresh inputs are accepted at one end before previously approved inputs emerge as outputs at the other end, this process is also known as pipelining.  To apply this approach to instruction execution, we must first acknowledge that instruction is divided into many phases. Consider the breakdown of instruction processing as follows. 1. Fetch instruction (FI): Read the next expected instruction into a buffer. 2. Decode instruction (DI): Determine the opcode and the operand specifiers. 3. Calculate operands (CO): Calculate the effective address of each source operand. This may involve displacement, register indirect, indirect, or other forms of address calculation. 4. Fetch operands (FO): Fetch each operand from memory. Operands in registers need not be fetched. 5. Execute instruction (EI): Perform the indicated operation and store the result, if any, in the specified destination operand location. 6. Write operand (WO): Store the result in memory.

Pipeline Hazards A pipeline danger arises when the pipeline, or a section of the pipeline, is forced to halt due to unforeseen circumstances. A pipeline bubble is another term for a pipeline standstill. Resources, data, and control are the three categories of dangers.

Resource Hazards When two (or more) instructions in the pipeline require the same resource, a resource hazard develops. As a result, during a section of the pipeline, the instructions must be performed in serial rather than parallel. A structural hazard is another name for a resource hazard.

Data Hazards When there is a conflict in the access to an operand location, a data hazard develops. The hazard can be stated in general words as follows: In a program, two instructions must be executed in order and must both address the same memory or register operand. There is no difficulty if the two instructions are executed in precise order. However, if the instructions are performed in a pipeline, the operand value may be modified in a way that produces a different result than if they were performed strictly sequentially. In other words, the usage of pipelining causes the program to provide an inaccurate result.

Control Hazards When the pipeline makes the erroneous judgment on a branch prediction, a control hazard, also known as a branch hazard, arises, bringing instructions into the pipeline that must be deleted....