CA Week 5 CPU - Structure and Function PDF

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Dr. Charles Fox...

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Week 5: CPU - Structure and Function

CPU Function: Basic instruction cycle:  Fetch-Decode-Execute Cycle  A program is executed sequentially o Instruction 1, instruction 2 etc o A clear and simple design o A speed bottleneck Control Unit:  Coordinates activities of the CPU o Instruction fetching/decoding o Execution management o Implemented in digital logic o Driven by a clock o A number of clock cycles is required to carry out each data movement or a computational operation o Very like a car timing belt: 24 October 2019 09:00

Von Neumann Architecture CPU Structure: Harvard Architecture  Memory + Bus  CPU: Arithmetic (and other) small machines + registers + control  Program + Data stored separately Von Neumann Architecture:  Memory + Bus  CPU: arithmetic ( and other) small machines + registers + control  Both data and program (instructions) stored in the same read/write memory

Registers: Small areas of memory inside the CPU, Temporary Storage Control Unit: Coordinates the work of everything else ALU: Performs operations on data Buses: Connects all the parts of the CPU together Analytical engine:  Barrel triggers  Like a music box/barrel organ LogiSim:  Temporal stages  Each pass control to next Registers:

User-visible data registers:  General purpose registers (eg, 16 in x86-64 architecture)  And/or accumulator  Width of data registers determines the architecture Internal Registers:  Program counter (PC) o Address of the instruction o Automatically incremented after each fetch execute cycle, so the CPU moves onto the next instruction  Instruction register (IR) o Stores the instruction being executed  Fast memory o Usually used in the CPU o Use clock to write values, stop clock to read o Typical implementation: D-type clip-flop array Arithmetic Logic Unit: Operations:  Integer addition, subtraction, multiplication, division  Logic operations (AND, OR, XOR, NOT)  Shift operations Input:  Data (A, B) Output:  Result of data operation (R)  Status of operation (D, Carry out , overflow etc)

Instruction Format: Each instruction is represented by  A unique number: opcode (operational Code)e.g. o Load/store/add data from memory to CPU o Halt, etc

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0, 1 or more operands (info about data to be manipulated) o Data location (e.g. Memory address, register) o Or data values

Stack Architectures: A stack is a simple data structure  Can be implemented entirely in SW  But many CPUs provide a HW stack Implementation:  Dedicate some are of memory o "stack overflow" if it overruns into rest of memory  CPU stack pointer register (SP)  CPU push, pop instructions o Eg, "PHA: Push accumulator to stack" o Autoincrement/decrement SP Applications  If fun out of register  Function calls - enable structured programming o Store return address o JSR, RTS - jump and return instructions o And push and pick up arguments  Operating systems... Assemblers: Assemblers translate instructions that are comprehensive to humans into the binary codes needed by computers  Mnemonic instructions, such as LOAD 50 are easier to remember, write and understand than a binary number  Specific to a CPU type  + other functions such as joining programs/libraries

Or macros which make them into simple compilers...

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Instruction Set Architecture: The instruction needs a clear indication of:  What the CPU has to do o Arithmetic operations o Movement of data o Program control  Where data involved in that operation is located o Where's the input stored? o Where should the output be stored? o Is data provided with the instruction? Needs to enable fast implementations Also need to be clear to human programmers  ISA design is the HW-SW interface

 o  o o o

4 bit opcode can represent max. 24 = 24 16 different instructions Modern CPU's might have hundreds of instructions - need more bits for the opcode Remaining bits (here 12) are left for the operand Usually an address in memory Can be also an immediate value of the operand (eg integer) 12-bit operand can represent 212 = 4096 different addresses or values

MARIE...