DDR4 Device Operations Rev11 Oct 14-0 PDF

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Rev. 1.1, Oct.2014

DDR4 SDRAM Specification CAUTION : The 3DS contents in this document includes some items still under discussion in JEDEC Therefore, those may be changed without pre-notice based on JEDEC progress In addition, it is highly recommended that you not send specs without Samsung’s permission

Device Operation & Timing Diagram SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2014 Samsung Electronics Co., Ltd. All rights reserved.

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Rev. 1.1

Device Operat ation Dev ice Oper at ion

DDR4 SDRAM

Revision History Revision No.

History

Draft Date

Remark

Editor

1.0

- First Spec release

Sep. 2014

-

J.Y.Lee

1.1

- Add 3DS Functional Description,3DS SDRAM Command Description and Operation

Oct. 2014

-

J.Y.Lee

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Rev. 1.1

Device Operat ation Dev ice Oper at ion

DDR4 SDRAM

Table Of Contents DDR4 SDRAM Specification 1. Functional Description .................................................................................................................................................. 6 1.1 Simplified State Diagram ..................................................................................................................................... 6 1.2 Basic Functionality................................................................................................................................................... 7 1.3 RESET and Initialization Procedure ........................................................................................................................ 8 1.3.1. Power-up Initialization Sequence..................................................................................................................... 8 1.3.2. VDD Slew rate at Power-up Initialization Sequence ........................................................................................ 9 1.3.3. Reset Initialization with Stable Power .............................................................................................................. 9 1.4 Register Definition ................................................................................................................................................... 11 1.4.1. Programming the mode registers ..................................................................................................................... 11 1.5 Mode Register ......................................................................................................................................................... 13 1.6 3DS Functional Description ..................................................................................................................................... 24 1.6.1. Simplified State Diagram.................................................................................................................................. 24 1.6.2. Basic Functionality ........................................................................................................................................... 24 1.6.3. Reset Signal and Initialization Procedure ........................................................................................................ 24 1.6.4. Mode Register Definition.................................................................................................................................. 24 2. DDR4 SDRAM Command Description and Operation .................................................................................................. 29 2.1 Command Truth Table............................................................................................................................................. 29 2.2 CKE Truth Table ...................................................................................................................................................... 30 2.3 Burst Length, Type and Order ................................................................................................................................. 31 2.3.1. BL8 Burst order with CRC Enabled.................................................................................................................. 31 2.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................... 32 2.4.1. DLL on/off switching procedure........................................................................................................................ 32 2.4.2. DLL “on” to DLL “off” Procedure....................................................................................................................... 32 2.4.3. DLL “off” to DLL “on” Procedure....................................................................................................................... 33 2.5 DLL-off Mode........................................................................................................................................................... 35 2.6 Input Clock Frequency Change ............................................................................................................................... 36 2.7 Write Leveling.......................................................................................................................................................... 37 2.7.1. DRAM setting for write leveling & DRAM termination function in that mode .................................................... 37 2.7.2. Procedure Description...................................................................................................................................... 38 2.7.3. Write Leveling Mode Exit ................................................................................................................................. 40 2.8 Temperature controlled Refresh modes .................................................................................................................. 40 2.8.1. Normal temperature mode ( 0°C =< TCASE =< 85°C ) .................................................................................. 40 2.8.2. Extended temperature mode ( 0°C =< TCASE =< 95°C )................................................................................ 40 2.9 Fine Granularity Refresh Mode ............................................................................................................................... 41 2.9.1. Mode Register and Command Truth Table...................................................................................................... 41 2.9.2. tREFI and tRFC parameters ............................................................................................................................ 41 2.9.3. Changing Refresh Rate.................................................................................................................................... 42 2.9.4. Usage with Temperature Controlled Refresh mode ......................................................................................... 42 2.9.5. Self Refresh entry and exit ............................................................................................................................... 43 2.10 Multi Purpose Register .......................................................................................................................................... 43 2.10.1. DQ Training with MPR ................................................................................................................................... 43 2.10.2. MR3 definition ................................................................................................................................................ 43 2.10.3. MPR Reads.................................................................................................................................................... 44 2.10.4. MPR Writes .................................................................................................................................................... 46 2.10.5. MPR Read Data format.................................................................................................................................. 49 2.11 Data Mask(DM), Data Bus Inversion (DBI) and TDQS.......................................................................................... 55 2.12 ZQ Calibration Commands .................................................................................................................................... 57 2.12.1. ZQ Calibration Description ............................................................................................................................. 57 2.13 DQ Vref Training.................................................................................................................................................... 59 2.13.1. Example scripts for VREFDQ Calibration Mode: ........................................................................................... 61 2.14 Per DRAM Addressability ...................................................................................................................................... 64 2.15 CAL Mode (CS_n to Command Address Latency)................................................................................................ 66 2.15.1. CAL Mode Description ................................................................................................................................... 66 2.15.2. Self Refresh Entry, Exit Timing with CAL....................................................................................................... 69 2.15.3. Power Down Entry, Exit Timing with CAL ...................................................................................................... 69 2.16 CRC....................................................................................................................................................................... 70 2.16.1. CRC Polynomial and logic equation............................................................................................................... 70 2.16.2. CRC data bit mapping for x8 devices............................................................................................................. 71 2.16.3. CRC data bit mapping for x4 devices............................................................................................................. 71

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2.16.4. CRC data bit mapping for x16 devices........................................................................................................... 71 2.16.5. Write CRC for x4, x8 and x16 devices ........................................................................................................... 72 2.16.6. CRC Error Handling ....................................................................................................................................... 72 2.16.7. CRC Frame format with BC4 ......................................................................................................................... 73 2.16.8. Simultaneous DM and CRC Functionality...................................................................................................... 76 2.16.9. Simultaneous MPR Write, Per DRAM Addressability and CRC Functionality ............................................... 76 2.17 Command Address Parity( CA Parity ) ................................................................................................................. 77 2.17.1. CA Parity Error Log Readout ......................................................................................................................... 82 2.18 Control Gear-down Mode ...................................................................................................................................... 82 2.19 DDR4 Key Core Timing ......................................................................................................................................... 85 2.20 Programmable Preamble....................................................................................................................................... 88 2.20.1. Write Preamble .............................................................................................................................................. 88 2.20.2. Read Preamble .............................................................................................................................................. 89 2.20.3. Read Preamble Training ................................................................................................................................ 90 2.21 Postamble.............................................................................................................................................................. 91 2.21.1. Read Postamble............................................................................................................................................. 91 2.21.2. Write Postamble............................................................................................................................................. 91 2.22 ACTIVATE Command ........................................................................................................................................... 92 2.23 Precharge Command ............................................................................................................................................ 92 2.24 Read Operation ..................................................................................................................................................... 92 2.24.1. READ Timing Definitions................................................................................................................................ 92 2.24.1.1 READ Timing; Clock to Data Strobe relationship ..................................................................................... 94 2.24.1.2 READ Timing; Data Strobe to Data relationship ....................................................................................... 95 2.24.1.3 tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation ............................................................................... 97 2.24.1.4 tRPRE Calculation .................................................................................................................................... 99 2.24.1.5 tRPST Calculation .................................................................................................................................... 100 2.24.2. READ Burst Operation ................................................................................................................................... 101 2.24.3. Burst Read Operation followed by a Precharge............................................................................................. 112 2.24.4. Burst Read Operation with Read DBI (Data Bus Inversion)........................................................................... 114 2.24.5. Burst Read Operation with Command/Address Parity ................................................................................... 115 2.24.6. Read to Write with Write CRC........................................................................................................................ 116 2.24.7. Read to Read with CS to CA Latency ............................................................................................................ 117 2.25 Write Operation ..................................................................................................................................................... 118 2.25.1. Write Timing Parameters ............................................................................................................................... 118 2.25.2. Write Data Mask............................................................................................................................................. 119 2.25.3. tWPRE Calculation......................................................................................................................................... 120 2.25.4. tWPST Calculation ......................................................................................................................................... 121 2.25.5. Write Burst Operation..................................................................................................................................... 122 2.25.6. Read and Write Command Interval ................................................................................................................ 138 2.25.7. Write Timing Violations .................................................................................................................................. 138 2.25.7.1 Motivation ................................................................................................................................................. 138 2.25.7.2 Data Setup and Hold Offset Violations ..................................................................................................... 138 2.25.7.3 Strobe and Strobe to Clock Timing Violations .......................................................................................... 138 2.26 Refresh Command ................................................................................................................................................ 139 2.27 Self refresh Operation ........................................................................................................................................... 141 2.27.1. Low Power Auto Self Refresh ........................................................................................................................ 142 2.27.2. Self Refresh Exit with No Operation command.............................................................................................. 143 2.28 Power down Mode................................................................................................................................................. 144 2.28.1. Power-Down Entry and Exit ........................................................................................................................... 144 2.28.2. Power-Down clarifications.............................................................................................................................. 149 2.28.3. Power Down Entry and Exit timing during Command/Address Parity Mode is Enable .................................. 150 2.29 Maximum Power Saving Mode.............................................................................................................................. 151 2.29.1. Maximum power saving mode ....................................................................................................................... 151 2.29.2. Mode entry ..........................................................................