Digital Electronics Lab file (D and T flip-flops) PDF

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Summary

VHDL code for the implementation of D and T flip-flops...

Description

PRACTICAL 3 Aim: Write down VHDL program for D flip flop. Apparatus: Xilinx ISE 14.7 System Description: The D Flip Flop is by far the most important of the clocked flip-flops as it ensures that ensures that inputs S and R are never equal to one at the same time. The D-type flip flop are constructed from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for a single D (data) input. Then this single data input, labelled D, is used in place of the “set” signal, and the inverter is used to generate the complementary “reset” input thereby making a level-sensitive D-type flip-flop from a level-sensitive RS-latch as now S = D and R = not D as shown.

D-type Flip-Flop Circuit

SCHEMATIC:

D-Flip Flop RTL Schematic VHDL CODE FOR D-FLIP FLOP library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Dfflop is Port (

clk : in STD_LOGIC; x : in STD_LOGIC; pr : in STD_LOGIC; clr : in STD_LOGIC; q : out STD_LOGIC) ;

end Dfflop; architecture Behavioral of Dfflop is begin process(clk,clr,pr) begin if ((pr = '1') and (clr ='1')) then q...