Fabrication and Layout PDF

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Fabrication and Layout

Kenneth Yun UC San Diego Adapted from EE271 notes, Stanford University

Overview n Semiconductor properties n How chips are made n Design rules for layout n Reading n Fabrication: W&E 3.1, 3.2.1, 3.3.1 n Design Rules: W&E 3.4-3.4.3

What To Build n Transistors n nMOS and pMOS

n Wires n Many levels of (real) metal wires

(aluminum and copper) n

Need low resistance (high conductivity)

n Oxide insulators between metal layers n Contacts (hole in the oxide) between

adjacent layers

Silicon n Semiconductor n Conductivity changed by adding impurities n Impurities, called dopants, create either n-

type or p-type regions

n Oxide is stable n SiO2 (quarz or glass) n Great for sealing things from impurities n Can be selectively patterned n Etching can remove SiO2 without harming

Si

Doping n Adding arsenic or phosphorous to

intrinsic silicon increases conductivity n By adding ‘free’ electrons n n-type since current is carried by

negatively charged particles (electrons)

n Adding boron to intrinsic silicon

increases conductivity n By adding ‘free’ holes n p-type since current is carried by positively

charged “particles”

Diode n Junction between n-type and p-type

regions form a diode

I n+

p+

p+

n

V

How To Build Transistor n Diffusion made by adding (diffusing)

impurities into silicon n n+ (p+) diffusion has lots of impurities

(dopants), so higher conductivity n p (n) regions lightly doped n p region formed first; n+ doped over parts

of p region n n+ dopant added after poly is down so

that poly blocks dopant poly n+

p

n+

Two Transistor Types n CMOS requires two types of substrates

for isolation of transistors g

n n-type for pMOS

cross

n p-type for nMOS

n+

p

n+

Substrate = p

s

p+

d

n

section

p+

Substrate = n

Well: Local Substrate n Base wafer type may be n n-type: add pwell / p-type: add nwell n Some have “twin” well

p+

n+ p

pwell process

n

n substrate

Well Requirement n Well must be tied to a power supply to

keep isolation diode reversed biased n Using well contacts (ohmic connection to

the well)

n+

p

Tied to GND

n+

p+

n

Tied to Vdd

p+

Well Contacts n Formed by placing p+ doped region in

pwell (n+ region in nwell) n These regions make good electrical

contact to the well (ohmic, not diode) n Well potential equal to the diffusion

potential

n Need to have at least one well contact

in each well

What’s On A Chip: Review n Transistors n Require silicon substrate, wells, two types

of diffusion, poly

n Wires n Many levels of (real) metal wires n Oxide insulator between metal layers n Contacts between adjacent layers

Fabrication Masks

Chips Processing Wafers

Processed Wafer

Basic Fabrication Steps n Transfer image of the design to wafer

(photolithography) n Create layers (diffusion/oxide/metal) n Ion implant for diffusion; shoot impurities

at silicon n Deposition for oxide/metal; usually

chemical vapor deposition (CVD) n Grow for oxide; place silicon in oxidizing

ambient

Basic Processing Start with wafer at current step Spi n on a photoresist

Pattern photoresist with mask Step specific processing etch, implant, etc... Wash off resist

IC Fabrication n Repeat n Create layer on wafer n Put photo-sensitive material (resist) on top of

wafer n Optically project image of pattern on water n Develop resist n Use resist as mask to prevent etch from reaching

layer below, when transferring pattern to layer n Remove resist

n All die on wafer processed in parallel; for

some chemical steps, many wafers processed in parallel

Photolithography n To transfer pattern onto wafer, first need an

image to project n Glass plate (mask) with image of pattern etched in

chrome generated from design database n

Mask = negative in photography

n Image optically projected onto wafer using

“projection aligner” n

projection aligner = enlarger in photography

n Mask allows printing on large number of

wafers n Cost per wafer low, assuming lots of wafers

Making Transistors 1. Implant N-Well

2. Define thin oxide; grow field oxide

3. Etch poly

Making Transistors 4. Implant threshold adjust

5. Implant source and drain

Making Wires

1. Deposit insulator; may be polished to make it fit

2. Etch contacts to Si; fill with conductor

3. Pattern metal wires

Foundry Interface

Designer

Layout (Mask Set)

Design Rules Process Parameters

Foundry

MAGIC MOSIS SCMOS Layers n 4 types of diffusion n Normal (forms transistor) n

ndiff

n

pdiff

n Diffusion for well contacts n

nohmic

n

pohmic

n Poly n Metal n M1 n M2

Physical and MAGIC Layers Physical Masks (simplified)

Magic Layers

nwell

nwell

active area (thin ox)

ndiff (active & nselect & ~nwell)

poly

pdiff (active & pselect & nwell)

threshold adjust (n & p)

nnd (active & nselect & nwell)

implant select (n & p)

ppd (active & pselect & ~nwell)

contact

poly

metal 1

metal1

via

metal2

metal 2

contacts

glass

Layer Example

MAGIC Contacts

+

+

=

ndc - ndiff to metal1 pdc - pdiff to metal1 ppc - ppd to metal1 nnc - nnd to metal1 pc - poly to metal1 via - metal1 to metal2

Contact Example

Fabrication Constraints On Layout n Resolution constraints n Smallest printable feature / smallest

spacing that guarantees no short n Depends on lithography and processing

steps n Resolution often depends on smoothness

of surface

n Alignment/overlap constraints n Need to align layers (like printing color

picture)

Geometric Design Rules n Resolution n width and spacing of lines

on one layer

n Alignment n to make sure interacting

layers overlap (or don’t) n contact surround n poly overlap of diff n well surround of diff n contact spacing to

unrelated geometry

3 3

MOSIS SCMOS Design Rules n Allow you to send designs to different fabs n Rules are based on

- half the drawn gate

length (poly width) n All other design rules expressed in multiples

of n Poly width = 2 , space = 3 n metal width = space = 3

n Conservative n Manhattan layout (only 90 degree angles)

SCMOS Design Rule Highlights n Resolution rules

Layer poly diff m1 m2 nwell cut via

Width 2 3 3 3 10 2 2

Space 3 3 3 4 9 2 3

n Alignment rules

cut/via surround poly overlap diff poly space to diff

1 2 1

Notes: Cut plus surround is 4 Layout falls on 8 grid

Pitch n Repeat distance between objects n 8

contacted transistor pitch n

cut + poly width + 2 x cut-to-poly

n 6.5 n

(contact + width)/2 + spacing

n 7.5 n

n 7

semi-contacted m1 pitch

semi-contacted m2 pitch

(contact + width)/2 + spacing

fully contacted m1 pitch n

n 8

contact + spacing

fully contacted m2 pitch n

contact + spacing

8

Contact Rules n Spacing from contacts is slightly larger

than from base material n Poly contact to poly spacing = 3 n Diffusion contact (ndc, pdc, nwc, pwc) to

diffusion = 4

n So that the fab can make surround of

contact cut slightly larger than 1 necessary

if

Magic Number “8” n Most of the important rules for

estimating the size of stick diagram can be approximated by 8

M2 w/c = 8

(diff width =4) diff w/c = 8 8

M1 w/c = 7 poly w/dc = 8 poly w/c = 7

Stick Diagrams n Like a layout n Basic topology of the circuit n Relative positions of objects roughly

correct

n But n Wires have no width n Size of objects not to scale n Missing wires can be squeezed in between

two wires

Layout Issues n Two types of diffusion n ndiff n

poly crossing ndiff makes nMOS transistor

n pdiff n

poly crossing pdiff makes pMOS transistor

n Cannot directly connect ndiff and pdiff n

must connect ndiff to metal and metal to pdiff

n Cannot get ndiff too close to pdiff because of wells n

large spacing rule between ndiff and pdiff

n

need to group nMOS transistors together and pMOS transistors together

Basic Layout Planning n Need to route power and ground (in metal) n Keep nMOS devices near nMOS devices and

pMOS devices near pMOS devices n nMOS near ground and pMOS near Vdd

n Run poly vertically and diffusion horizontally

with m1 horizontally n Keep diffusion wires as short as possible n just enough to make transistors

n All long wires in m1 and m2

Typical Cell Layout Plan n Parity

n Inverter

Vdd Gnd...