FPGA implementation of a single-channel HDLC Layer-2 protocol transmitter using VHDL PDF

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See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/4069202 FPGA implementation of a single-channel HDLC Layer-2 protocol transmitter using VHDL Conference Paper · December 2003 DOI: 10.1109/ICM.2003.1287796 · Source: IEEE Xplore CITATIONS RE...

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FPGA implementation of a singlechannel HDLC Layer-2 protocol transmitter using VHDL Syed Manzoor Qasim … , 2003. ICM 2003. Proceedings of the …

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See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/4069202

FPGA implementation of a single-channel HDLC Layer-2 protocol transmitter using VHDL Conference Paper · December 2003 DOI: 10.1109/ICM.2003.1287796 · Source: IEEE Xplore

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ICM 2003,Dec. 9-1 1, Cairo, Egypt.

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FPGA Implementation of a Single-Channel HDLC Layer-2 Protocol Transmitter using VHDL Syed Manzoor Qasim and Shuja A. Abbasi

Department of Electrical Engg., King Saud University, P. 0. Box -800, Riyadh - 11421, Saudi Arabia [email protected] ABSTRACT

To successfilly transmit data over any network, a protocol is required to manage the flow or pace at which the data is transmitted. This protocol is defined in Layer 2 of OS1 (Open Systems Interconnection) model. High-level Data Link Control (HDLC) is the most commonly used Layer 2 protocol and is suitable for bit oriented packet transmission mode. This paper discusses thc VHDL modeling of single-channel HDLC Layer 2 protocol Transmitter and its implementation using Xilinx Virtex FPGA as the target technology. The HDLC Transmitter is used to transmit the HDLC frame structure. Implementing the single-channel HDLC protocol Transmitter in FPGA gives you the flexibility] upgradability and customization benefits of programmable logic.

and specific bit patterns used for control differ dramatically from those in representing data, which reduces the chances of errors [IO].

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Each piece of data is encapsulated in an HDLC frame by adding a trailer and a header. The header contains an HDLC address and an HDLC control field [9]. The trailer is found at the end of the frame, and contains a Cyclic Redundancy Check (CRC), which detects any errors, which may occur during transmission. The frames are separated by HDLC flag sequences, which are transmitted between each frame and whenever there is no data to be transmitted.

I . INTRODUCTION

High level Data Link Control, also known, as HDLC is a bit oriented, switched and non-switched protocol. It is a data link control protocol and falls within layer 2, the Data link layer, of the Open Systems Interconnection (0%) model [101.

Flag

for

Data

FCS

Flag

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This figure does not include bits inserted for transparency. Transparency (Zero stuffing) is performed on the HDLC packets whenever five contiguous "I bits are transmitted. The fields are transmitted from left to right, least significant bit first [4]. Each frame start and end with a flag sequence (01 1 I 1 1 IO). It is used for frame synchronization. The Address field [4] is of programmable size (8bits or 16-bits). The data field may contain any number of bits. The Frame Check Sequence (FCS) field contains a 16-bit or 32-bit Cyclic Redundancy

HDLC is a protocol developed by the International Organization

Address

standardization

(ISO).It falls under the IS0 Standards IS0 3309 and IS0 4335. It has been found itself being used throughout the world. It has been so widely implemented because it supports both half duplex and full duplex communication lines, point to point (peer to peer) and multipoint networks, and switched and non-switched channels. The procedures outlined in HDLC are designed to permit synchronous, code-transparent data transmission, Other benefits of HDLC are that the control information is always in the same position

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Check (CRC). The FCS is transmitted least significant octet first, which contains the coefficient of highest term in the generated check polynomial. It is used for error detection. 3. SYSTEM DESCRIPTION

f system t initialization, ~ ~ the HDLC ~~~~~i~~~ checks the transmit Register and waits until transmitter is enabled. Once transmitter is enabled, transmit data is loaded into the transmit register on the rising edge of clock from the external CPU. The transmitter controller will send a signal to the transmit register module to send the data. On receipt of the first byte of a new packet, the controller will issue the appropriate flag sequence (01 1 1 1 110) and transmit the frame data calculating the FCS. The FCS is a 16/32-bit Cyclic Redundancy Check (CRC) and is computed using a 16/32-bit linear feedback shift register. When the last byte [4] of the frame is seen, the FCS is transmitted along with a closing flag (01 11 1 1 IO). Extra zeros are inserted by the bit stuffer into the bit stream to avoid transmission of the control flag sequences within the frame data. ~

a

The transmit data is available as serial output on the TxD pin. If the TxEN pin is deasserted, the transmit pipeline is stalled, and the TxlD pin is disabled. At any time the transmission of a frame can be aborted by sending the Abort flag, which is (01111111). We assume that the input data and control signals are coming from an extemal host CPU. The address control is loaded after TxEN= '1 and before TxFrameStart signal is asserted. 4. SYSTEM IMPLEMENTATION

The HDLC Transmitter consists of the following main blocks as shown in Fig.2.

I . Transmitter Controller. 2. Transmit Register. 3. Address Insertion. 4. Frame Check Sequence (FCS) generation 5 . Bit Stuffer 6. Flag/Abort Generation.

HDLC Transmitter controlller is responsible for generating all the necessary internal control signals

Tx Frame Signal Delay Bit Stuffer

TxD

FCS

Delay

L

Address Signals

L Address lnsertion

Control Innuts

I -' '

FlaglAbort Generation

Tx Control Register

Fig. 2: System Block Diagram

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required different : modules. It is implemen g a Finite State Machine approach. lay element are implemented using D Transmit egister module 1s responsible fd,bpturing the data on the rising ed e of the clock. The address field is of programmab B size, eith,er 8-bit or 16-bit. The field can contain the value programmed into the transmit address register at the time the frame is started [4]. The address insertion module will insert the HDLC Frame address into the frame structure and forward the data along with the address to the other modules for further processing. This can be My arbitrary address, or the broadcast or “All-Stations” Address, which are all ones [4]. The Frame Check Sequence (FCS) generation module is used to calculate a CRC across the transmitted message. Two different polynomials can be selected. The 16-bit FCS [lo] uses the polynomial (x16 + x12 + x5 + 1) and the 32-bit FCS [lo] uses the polynomial (x32+ x26+ x23+ x22+ xI6 + x 2 + x” .t x’O+ x8+ x’+ x5+ x4+ x*+ x 1). Bit Stuffer is responsible for examining the frame content between the opening and closing flags and checking for 5 consecutive ‘1 bits, including the FCS bits. If 5 consecutive ‘ 1 bits are detected, a ‘0 bit is inserted into the serial transmission. This will help the receiver to distinguish between an opening and closing flag and actual data. The flag/Abort generation module will generate the opening flag as soon as the data is available. After the last byte of FCS has been transmitted, a closing flag is sent. At any time the transmission of a frame can be aborted by sending the abort flag, which is (01 11 11 1I). Each module of the HDLC transmitter has been modeled, simulated and synthesized using VHDL. Finally all the blocks were integrated using port mapping technique in VHDL in order to get the complete HDLC Transmitter.

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Table 1: Device Utilization for v50bg256

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S. RESULTS The design was coded in VHDL and successfully implemented in Xilinx Virtex FPGA. ModelSim from Mentor Graphics was the tool used for presynthesis and post-synthesis simulation and Leonard0 Spectrum from Exemplar logic was used for synthesis. The final implementation of the design on the target Virtex FPGA was done using

Xilinx Foundation Series suite of software. The reason for using Virtex FPGA is its various built-in features that solve designer’s challenge throughout the system. This family provides a broad capability for chip-to-chip communications through programmable support for the latest I/O standards, digital Delay-Locked Loops (DLLs) for clock signal synchronization on the FPGA and on the board, and a memory hierarchy to manage fast access to RAM on and off chip. Table 1 summarizes the device utilization for virtex (v50bg256) FPGA with a speed grade of -4. The single channel HDLC Transmitter is found to be running at a frequency of 59.2 MHz with a total equivalent gate count of 574. 6. CONCLUSION

In this project, single channel HDLC Protocol Transmitter has been successfidly implemented in Xilinx Virtex series FPGA. During the development of the VHDL code, it has been a goal to make it synthesizable. By synthesizing the design, some constraints on area and timing have been found. These increase linearly with increasing input parameters and that are taken as a proof that the VHDL model could be synthesized well [111. Each module of the transmitter is thoroughly simulated both before and after synthesis and is well optimized. The advantage of implementing this HDLC Protocol Transmitter in FPGA is that it gives you the flexibility, upgradability and customization benefits of programmable logic devices. This Single Channel HDLC Protocol Transmitter is a high performance module for the

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bit-oriented packet transmission mode. It is suitable for Frame Relay switches, Video conferencing on ISDN, ISDN B-channel C D-Channel, SONET Termination, X.25 layer-2 protocol, Cable Modem, Private packet data networks & switches [7].

7.REFEVNCES

[I] K.C&hang, “Digiful Design & Modeling with VHDL and Synthesis”, IEEE Computer Society Press, 1997. [2] J.F.Wakerly, “Digital Design principles & practices ”, Prentice Hall, New Jersey, 2000. [3] Z.Navabi, “VHDL Anaiysis & Modeling of Digital systems”, McGraw Hill Inc., 1993. [4] Xilinx Application Note,; “Single-Ch’anid HDLC Core v2.0 , Xilinx Inc., 2tOl.

[SI “The Programmable Logic Data Book”, Xilinx

Inc., 1996. [6] Z.Navabi, “VHDL Analysis & Modeling of Digital systems”, McGraw Hill Inc., 1993. [7] A.Tannenbaum, “[Computer Networks ”, Prentice Hall of India, 1993. [8] D.Bertsekas & RGallager, “Data Networks”, Englewood Cliffs, N.J.,Prentice Hall, 1992. [9]U.Black, “Data Link Protocols”, Englewood Cliffs, N.J., Prentice Hall, 1993. [IO] William Stallings, “Data & Computer Communications”, Prentice Hall of India, 2000. [I I ] Michael Gschwind & Valentina ?alapura, “ VHDL Design Methpdoiology for FPGAs ”, Technische Universitat WiCn. [12] Michael Gschwind k~ Valentina Salapura, “Optimizing VHDL for FPCA Targets”, Technische Universitat Wien.

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