Glossary of Fault Models PDF

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Unit I: Introduction to Testing & Verification

2020

A Glossary of Fault Models Assertion Fault:

An assertion fault means that the corresponding property is not “true” for some input of the system. This fault model has been used for generating tests for a microprocessor

Behavioral Faults:

When the behavior of an electronic system is described in computer-readable form, it is generally written in a programming language (such as C) or some other hardware description language that resembles a programming language. At the behavioral level, also referred to as functional or high level, the variables or operations are not necessarily electrical, but correspond to the specific application domain. Behavioral faults refer to incorrect execution of the language constructs used in the description.

Branch Fault: This fault is modeled at the behavioral level where the circuit function is described in a programming language. A branch fault affects a branch statement and causes it to branch

to

an

incorrect

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Unit I: Introduction to Testing & Verification

Bridging Fault: Usually modeled at the gate or transistor level, a bridging fault represents a short between a group of signals. The logic value of the shorted net may be modeled as 1dominant (OR bridge), 0-dominant (AND bridge), or indeterminate, depending upon the

technology

in

which

the

circuit

is

implemented.

Bus Fault: A bus fault specifies the status for each line in a bus as stuck-at-0, stuck-at-1, or faultfree.

Cross-point Fault: These faults are modeled in programmable logic arrays. In the layout of a PLA, input and output variable lines are laid out perpendicular to the product-lines. Crossing signal lines either form specific types of connections or remain unconnected at crosspoints,

depending

on

the

function

implemented.

There are two types of cross-point faults. A missing cross-point means a missing connection at a crossing where a connection was intended. An extra cross-point means a faulty connection at a crossing where no connection was intended.

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Defect-Oriented Faults: Faults at the physical level that usually occur during manufacture are called defects. The electrical or logic-level faults that can be produced by physical defects are classified as defect-oriented faults.

Delay Fault: These faults cause the combinational delay of a circuit to exceed the clock period. Specific delay faults are transition faults, gate-delay faults, line-delay faults, segmentdelay faults, and path-delay faults.

Gate-Delay Fault: The fault increases the input to output delay of a single logic gate, while all other gates retain some nominal values of delay. The increase in the delay of the faulty gate is called the size of the gate-delay fault.

Hyperactive Fault: A hyperactive fault causes a large number of signals in the circuit to differ from their correct values. The fault thus produces very high fault related activity in the circuit. If not readily detected, fault simulators usually remove hyperactive faults for later consideration

to

save

CPU

time

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and

memory.

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Unit I: Introduction to Testing & Verification

Initialization Fault: Circuits with memory elements (e.g., flip-flops) are designed so that they can be initialized by applying suitable input signals. initialization

procedure

are

Faults that interfere with such an called

initialization

faults.

Example: Initialization Fault - In the circuit of Figure, consider a fault that permanently grounds the signal A. Such a fault is called a stuck-at-0 fault and will be

discussed

in

detail.

In

our

notation,

where

the

faulty

value

differs from the correct value, the faulty value is shown in parentheses. We assume that the initial state of the circuit (i.e., output Q of the flip-flop FF) is unknown, denoted as X. To set Q to 0, we apply A = 1 and B = 0. After the application of the clock CK, the fault-free circuit output is initialized to 0, but the faulty circuit remains in the unknown state. Such a fault that prevents the circuit from being initialized is called an initialization fault.

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Instruction Fault: Usually modeled in programmable systems like microprocessors or digital signal processors, an instruction fault causes an intended instruction to be incorrectly executed. Commonly considered faulty cases involve a target instruction producing a wrong

result

or

the

execution

of

an

unintended

instruction

Intermittent Fault: A fault that appears and disappears as a function of time is called an intermittent fault. A fracture in an interconnection may produce an intermittent open for some time before it becomes a permanent fault.

Line-Delay Fault: This fault models rising and falling delays of a given signal line.In contrast with the transition fault where the transition can be propagated through any path, a test for a line-delay fault must propagate the transition through the longest sensitizable path.

Logical Faults: These faults affect the state of logic signals. Normally, the state may be modeled as {0, 1, X (unknown), Z (high impedance)}, and a fault can transform the correct value to 5 Department of Electronics & Communication Engineering

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any other value. Several types of faults can be modeled at the logic level. However, the term logical fault often implies stuck-at faults.

Memory Faults: Faults modeled in memory blocks are single cell stuck-at-[0,l] faults, pattern sensitive faults, cell coupling faults, and single stuck-at faults in the address decoder logic.

Multiple Faults: A multiple fault represents a condition caused by the simultaneous presence of a group of single faults. Frequently considered multiple faults consist of the same type of single faults. For example, multiple stuck-at faults, or multiply-testable path-delay faults. Multiple stuck-at faults are usually not considered in practice because of two reasons:

1. The number of multiple stuck-at faults in a circuit with n single fault sites is 3^(n) – 1 which is too large a number even for circuits of moderate size.

2. Tests for single stuck-at faults are known to cover a very high percentage (greater than 99.6%) of multiple stuck-at faults when the circuit is large and has several outputs.

Non-classical Fault: Although a non-classical fault, in general, refers to a fault other than a stuck-at fault, 6 Department of Electronics & Communication Engineering

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the term has been used for the stuck-open and stuck-short faults of MOS technologies.

Parametric Fault: Such a fault changes the values of electrical parameters of active or passive devices from their nominal or expected values. Examples are the threshold voltage of a transistor (active device) and values of resistors and capacitors (passive devices).

Path-Delay Fault: This fault causes the cumulative propagation delay of a combinational path to increase beyond some specified time duration. The combinational path begins at a primary input or a clocked flip-flop, contains a connected chain of logic gates, and ends at a primary output or a clocked flip-flop.

Pattern Sensitive Fault: This fault causes an incorrect behavior in a certain part of the circuit only when a specific state occurs in some other part. Usually modeled in memories, a typical example is a fault condition that prevents writing a 1 in a memory cell when its physical neighbors have 0s stored in them.

Permanent Fault: Any faulty behavior that does not change with time is called a permanent fault. Faults that are not permanent and affect the circuit only at certain times (often at random instants) are called intermittent faults. 7 Department of Electronics & Communication Engineering

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Physical Faults: These faults cause physical changes in the circuit. Examples of physical faults are broken

wires,

bridges

(shorts)

between

conductors

carrying

unconnected si.gnals, shorted or open transistors, etc. These faults also sometimes referred to as “defect-oriented faults”

Pin Fault: When a circuit is modeled as an interconnect of modules, the terminals of those modules are referred to as pins. This term is adopted from the technology of printed circuit boards (PCBs), which contain interconnecting wiring between the pins of the mounted chips. Pin faults are the stuck-at faults on the signal pins (not power and ground

pins)

of

all

modules

in

the

circuit.

PLA Faults: A programmable logic array (PLA) is a physical implementation of two-level AND-OR combinational logic. The design consists of three sets of parallel wires: inputs, product-terms, and outputs. Three types of faults are modeled in a PLA:

1. Stuck-at faults on inputs and outputs. 8 Department of Electronics & Communication Engineering

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2. Cross-point faults 3. Bridging faults

Potentially Detectable Fault: When a test is applied to a sequential circuit, certain faults produce an unknown state at the output when a deterministic output is expected in the fault-free circuit. This condition is known as potential (or probabilistic) detection. In contrast, deterministic detection requires that both faulty and fault-free outputs be different and definite (0 or 1.) Generally, stuck-at faults that can only be detected potentially are called potentially detectable faults.

Quiescent Current Fault: •

These faults are relevant to the CMOS technology. In the steady state the CMOS logic gate provides no conducting path between the power supply and ground.

•

Thus, the steady state current, also known as the leakage or quiescent current, of a CMOS gate is on the order of only a few microamperes.

Under various fault conditions in the gate, this current can rise by several orders of magnitude

thus

allowing

fault

detection

via

measurement. Faults detectable by this method are called IDDQ faults.

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Race Fault: Stuck-at faults that cause a race condition in the circuit are called race faults. For a certain initial state and input, the final state of an asynchronous sequential circuit can vary depending on specific delays of its logic gates. Such a condition is known as a race. Sometimes, race and oscillation faults are grouped together as star-faults.

Redundant Fault: Consider a combinational circuit. Any fault that does not modify the input-output function of the circuit is called a redundant fault. A redundant fault cannot be detected by any test. Such faults can be removed from the circuit without changing its output function. Removal of redundant stuck-at faults is often used for circuit optimization. In general, the faults in sequential circuits for which no test can be found are classified as untestable faults. Redundant faults form a subset

among

untestable

faults.

Segment-Delay Fault: A segment of length L is a chain of L combinational gates. Such a segment can be contained in one or more input to output paths. A segment-delay fault increases the delay of a segment such that all paths containing the segment will have a path-delay fault.

Structural Faults: 1 Department of Electronics & Communication Engineering

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The structure of a circuit may refer to its topology or to physical geometry. However, the term structural faults is commonly used not for faults modeled in the layout, but rather in gate-level interconnects. Examples of structural faults are single stuck-at faults and bridging faults.

This fault is modeled by assigning a fixed (0 or 1) value to a signal line in the circuit. A signal line is an input or an output of a logic gate or a flip-flop. The most popular forms are the single stuck-at faults, i.e., two faults per line, stuck at-1 (s-a-1 or sal) and stuck-at-0 (s-a-0 or sa0).

Stuck-Open and Stuck-Short Faults: Considering a MOS transistor as an ideal switch, a defect is modeled as the switch being permanently in either the open or the shorted state.In general, a MOS logic gate consists of more than one transistor. This fault model assumes just one transistor to be stuck-open or stuck-short. Stuck-short is also referred to as stuck-on or stuck closed.

Transistor Faults: Stuck-open and stuck-short faults are generally referred to as transistor faults Transition Fault: It is assumed that in the fault-free circuit all gates have some nominal delays and that the delay of a single gate has changed. The gate delay, usually an increase over the 1 Department of Electronics & Communication Engineering

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nominal value, is assumed to be large enough to prevent a passing transition from reaching any output within the clock period, even when the transition propagates through the shortest path. Possible transition faults of a gate are slow-to -rise and slow-to -fall types and hence the total

number

of

transition

faults is

twice the

number

of

gates.

Untestable Fault: A fault for which no test can be found is called an untestable fault. There are two classes of untestable faults:

1. Faults that are redundant, i.e., whose presence does not change the input/output behavior of the circuit.

2. Faults that change the input-output behavior of the circuit but no test can be found by a given method of testing or test generation. Initialization faults of sequential circuits belong to this class.

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