HW6 Solution Computer Architecture PDF

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HW1 Solution Computer Architecture...

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Q1. Explain how cache improves machine performance? Ans: Cache improves performance of the machine by reducing the number of memory reads that hit the main memory. A cache, which is small amount and high-speed memory, is where a processor stores that data it uses most often. Just like you put your kitchenware on the kitchen table when you are dining, a computer puts the data it needs to use for a specific application in its cache. If a new application arises that requires heavy use of different data, a processor will bring new data into the cache memory so it can perform the tasks that require this data more efficiently. The more cache the CPU has, the less time the computer spends accessing slower main memory and as a result programs may run faster.

Q2. List pros and cons of both write-through and write-back policies. Ans: Write-through Pros: - It helps in data recovery (In case of power outage or system failure). - It solves the inconsistency problem. - Main memory always has the most current copy of the data - Easy to implement. Cons: -In write through, data write will experience latency (delay) as we have to write to two locations (both Memory and Cache) - write is slower - every write needs a main memory access - as a result uses more memory bandwidth

Write-back Pros: - writes occur at the speed of the cache memory - multiple writes within a block require only one write to main memory - as a result uses less memory bandwidth Cons: - harder to implement - main memory is not always consistent with cache - reads that result in replacement may cause writes of dirty blocks to main memory

Q3. Assume that the machine has a 128KB cache with a 32-bit address. 3.1. Show the address decomposition of a direct-mapped cache (assume 16 bytes per block). Show your work. Tag

Index

Offset

Ans: # blocks in cache = 128×1024 / 16 = 8192 (2^13) So, #bits in index = 13 bits #bits in offset = log2 (16) = 4 bits #bits in tag = total address bits - #of bits in index - #bits in offset =32 – 13 – 4 = 15 bits

So, 31

17 TAG 15

16

4

3

Index 13

0 Offset 4

3.2. Show the address decomposition of a 4-way associative cache (assume 32 bytes per block). Show your work. Tag

Index

Offset

Ans: # bits in block offset = 5 (since each block contains 2^5 bytes) # blocks in cache = 128×1024 / 32 = 4096 (2^12) # sets in cache = 4096 / 4 = 1024 (2^10) sets (a set is 4 blocks kept in the cache for each index) So # bits in index field = 10 # bits in tag field = Address bits – Offset bits – Index bits = 32 – 5 – 10 = 17

So, Tag 17

Index 10

Offset 5

Q4. Consider following bits of the address used to access the cache using "direct-mapped cache" with 32bit address (4 bytes word size). TAG Index Offset 31-12 11-5

4-0

Also, assume that following byte-address cache references are recorded for problems, 4.3 and 4.4. 24 - 48 - 0 - 4 - 10244 - 10240 - 30 - 60 - 2100 – 3100

4.1. How many words (integer) can be stored in a single cache block in this machine? Hint) offset bits. Ans: As given Offset bits =5 Block size is 2^5 = 32 bytes As we given that word size = 4 byte So, 32 bytes = 8 words.

Q4.2. How many entries does the cache have? Hint) index bits.

Ans: As given Index bits = 7 2^7 = 128 sets As we know that, each set has 1 entry So, The cache have 128 entries.

Q4.3. How many blocks are replaced and what is hit ratio? Show your work. Also, show miss types (cold, conflict, and capacity). Ans: -

Blocks replaced = None Hit ratio = 3/10 Miss ratio = 7/10 (Compulsory miss = 1 , Capacity miss = 3 , Conflict miss = 3 )

Q4.4. How many blocks are replaced and what is hit ratio if the machine uses 2 way-associative cache? Show your work. Also, show miss types. Ans: -

Blocks replaced = None Hit ratio = 3/10 Miss ratio = 7/10 (Compulsory miss = 1 , Capacity miss = 3 , Conflict miss = 3 )

Q5.1 Get average memory access time (AMAT) with L1 cache alone. Ans: As given, L1 hit rate: 95% L1 Miss rate = 1 - 95/100 = 0.05 L1 hit time: 1 cycle Miss rate penalty: 500 cycles We know that, AMAT = Hit time + Miss rate x Miss penalty So, AMAT = 1 + 0.05 x 500 = 26 ns

Q5.2 Get average memory access time (AMAT) with L1/L2 caches. Ans: As given, L2 hit rate: 99% L2 Miss rate = 1 – 99/100 = 0.01 L2 hit time: 10 cycles Miss rate penalty: 500 cycles So, AMAT = Hit TimeL1 + Miss RateL1 x (Hit TimeL2 + Miss RateL2 x Miss PenaltyL2 ) AMAT = 1 + 0.05 x ( 10 + 0.01 x 500 ) = 1 + 0.05 x 15 = 1.75 ns

Q5.3 Get average memory access time (AMAT) with L1/L2/L3 caches. Ans: As given, L3 hit rate: 99% L3 Miss rate = 1 – 99/100 = 0.01 L3 hit time: 30 cycles Miss rate penalty: 500 cycles As we know that, AMAT for all three L1, L2 and L3 cache levels AMAT = Hit TimeL1 + Miss RateL1 [ Hit TimeL2 + Miss RateL2{ Hit TimeL3 + Miss RateL3(Miss PenaltyL3)}] So, AMAT = 1 + 0.05 x [ 10 + 0.01 { 30 + 0.01 (500)}] AMAT = 1 + 0.05 x [ 10 + 0.01 { 35}] AMAT = 1 + 0.05 x [ 10.35] = 1.51 ns...