HW7 - EE-2513-0A1-Spring-2021- Logic Design Paul Morton PDF

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EE-2513-0A1-Spring-2021- Logic Design
Paul Morton...

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Stefany Pascua HW7 - Fundamentals of Logic Design by Charles H. Roth, Larry L. Kinney 8.1 Complete the timing diagram for the given circuit. Assume that both gates have a propagation delay of 5 ns.

8.3 For the following circuit: (a) Assume that the inverters have a delay of 1ns and the other gates have a delay of 2 ns. Initially A = 0 and B = C = D = 1, and C changes to 0 at time = 2 ns. Draw a timing diagram and identify the transient that occurs.

(b) Modify the circuit to eliminate the hazard.

G = BC + C’AD + A’BD 9.1 (a) Show how two 2-to-1 multiplexers (with no added gates) could be connected to form a 3-to-1 MUX. Input selection should be as follows: If AB = 00, select I0 If AB = 01, select I1 If AB = 1− (B is a don’t-care), select I2

9.7 An adder for Gray-coded-decimal digits (see Table 1-2) is to be designed using a ROM. The adder should add two Gray-coded digits and give the Gray-coded sum and a carry. For example, 1011 + 1010 = 0010 with a carry of 1(7 + 6 = 13). Draw a block diagram showing the required ROM inputs and outputs. What size ROM is required? Indicate how the truth table for the ROM would be specified by giving some typical rows.

ROM size = 28 * 5 = 1280 bits

The total size of the ROM is 1280 bits. 9.8 The following PLA will be used to implement the following equations: X = AB′D + A′C′ + BC + C′D′ Y = A′C′ + AC + C′D′ Z = CD + A′C′ + AB′D (a) Indicate the connections that will be made to program the PLA to implement these equations.

(b) Specify the truth table for a ROM which realizes these same equations.

9.25 Show how to make an 8-to-1 MUX using two 4-to-1 MUXes, two three-state buffers, and one inverter....