ISA/Microarchitecture PDF

Preview

Summary

These are a continuation of the discussion of the ISA, and dives into how the ISA is implemented within a CPU, via the microarchitecture...

Description

B format instruction type deals with the control flow of the program (conditional branching)  opcode is 6 bits  BR_address is 26 bits  B L1 o branch unconditionally to instruction labeled L1  B opcode = 000101 (base 2) in ARMv8  Effect: PC = PC + BranchAddress  BranchAddress = { 36{BR_address[25]}, BR_address, 2’b0} CB format instruction type opcode is 8 bits  COND_BR_address is next 19 bits  Rt is last 5 bits  branch to a labeled instruction if a condition is true (otherwise, continue sequentially)  exampleso CBZ register, L1 o if (register == 0), branch to instruction L1 o CBNZ register, L1 o if (register != 0), branch to instruction L1  effect: if you take the branch, PC = PC + CondBranchAddr; else PC = PC + 4  CondBranchAddr = { 43{COND_BR_address[18]}, COND_BR_address, 2’b0} Sometimes, you can have more conditions which are represented by conditional codes (CC) CC are set by arithmetic instructions with the S-suffix (ADDS, ADDIS, ANDS, ANDIS, SUBS, SUBIS)  negative (N): result had 1 in MSB  zero (Z): result was 0  overflow (V): result overflowed  carry (C): result had carryout from MSB Conditional branch is based on CC: B.cond (CB format) ISA Support for Functions Branch and Link (call): BL ProcedureAddress (B format) o PC  PC + BranchAddr o return address = old PC + 4 o GPR[X30]  return address o on a function call, the callee needs to know where to go back to afterwards o X30 is called the LR or link register  Branch to Register (ret): BR Rd (R format) o target = GPR[Rd] o PC  target

o allows the same instruction to jump to any location specified by Rd (X30 for return) WI Format Instructions  opcode is 9 bits  op2 is next 2 bits (determines which of the 4 16-bit portions you put the immediate in)  immediate is next 16 bits  Rd is last 5 bits  most constants are small (12-bit immediate is sufficient)  for the occasionally large constants, o movz: move wide with zeros // change other quarters to 0 o movk: move wide with keep // keep other 3 quarters  set any one of the 4 16-bit portions in Register RD with the immediate Logic Design Basics digital systems, information encoded in binary o one wire per bit, low voltage = 0; high voltage = 1  clock: measures the speed of the processor  logic elements o combinational logic (CL)- calculates the output of a logic function based on inputs o examples AND-gate (Y = A & B)  Adder (Y = A + B)  Multiplexer (Y = S ? l1: l0)  Arithmetic/Logic Unit (Y = F(A, B)) o state (sequential) elements- directly connected to CL to store circuit states  register: “remembers” data in a circuit (uses a clock signal to determine when to update the stored value; edge-triggered: update when clock changes from 0 to 1) // called flip-flop too  memory elements- large storage; a separate structure from logic elements Critical Path combinational logic (CL) computes and transform data o between clock edges o input from state elements, output to state element o longest delay determines clock cycle time  longest CL is called the critical path Memory elements inputs- address, read enable (re), write enable (we), write data (often coming from sequential elements)  output: read data (will often be stored in sequential elements)  can have multiple read/write “ports”



synchronous with the clock

How does a machine process instructions?  AS = architectural state (programmer visible) before an instruction is processed  AS’ = architectural state (programmer visible) after an instruction is processed  processing an instruction: transforming AS to AS’ according to ISA-specific functions of the program  registers, program counter, memory are all visible o as are the programs/instructions  instruction processing (ISA species what AS’ should be, given an instruction and AS)  the microarchitecture implements how AS is transformed to AS’ o you can have programmer-invisible states to optimize the speed of instruction execution (use one clock cycle or multiple clock cycles) Most basic instruction processing engine each instruction takes a single clock cycle to execute  only combinational logic is used to implement instruction execution  AS -> combinational logic -> AS’ Datapath vs Control Logic  combinational logic in an instruction processing engine consists of two components  datapath- consists of hardware elements that deal with and transform data signals o functional units that operate on data o hardware structures that enable the flow of data into function units/registers o storage units that store data (registers)  control logico consists of hardware elements that determine control signals, i.e., signals that specify what the datapath elements do to the data o an example is the block that generates the select signal for the mux For the single-cycle microarchitecture (uarch), assume:  “magic” memory and register file (RF)  combinational read o output of the read data port is a combinational function of the RF/mem contents and the corresponding read select port o read value shows up “immediately”  synchronous write o selected register/mem is updated on the positive edge clock transition when write enable is asserted o write value shows up in the next cycle o cannot affect read cycle in the current cycle Five steps to implement the LEGv8 ISA-

    

instruction fetch instruction decode and register operand fetch (ID/RF) execute/evaluate memory address (EX/AG) memory operand fetch (MEM) store/writeback result (WB)

If we use the R-type ADD instruction: (ADD Datapath)...