Lab3 - Lab Report PDF

Preview

Summary

Lab Report...

Description

NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York SUMMER, 2019

Component and Subsystem Design II CET 4805 SECTION D485 Meeting Day: Tuesday thru Thursday INSTRUCTOR: Prof. Y. WANG STUDENT: Urgiles, Cristhian

Design Multi-bit Multiplexer and Programming a FPGA Submission Date 07/29/2019

Lab Objective To familiarize oneself with different implementation methods to designing an 8-bit wide 2-to-1 multiplexer, a 3-bit wide 5-to-1 multiplexer and a 3-bit wide 6-to-1 multiplexer.

Lab Overview This lab experiment consisted of three parts. In part I we are to design an 8-bit wide 2-to1 multiplexer by exploring any of the three given code implementations which varies on the statements used to execute the code. In part II we are to design a 3-bit wide 5-to-1 multiplexer with the given implementation along with our preferred code. Lastly, in part III we are to design a 3bit wide 6-to-1 multiplexer using external switches and LEDs connected them to the GPIOs pins.

Lab Implementation 1. In part I of the lab experiment we are to design an 8-bit wide 2-to-1 multiplexer. We can achieve this by first understanding the sum-of-products circuit that implements a 2-to-1 multiplexer with a select input s. Furthermore, in our design when s = 0, the multiplexer’s output m is equal to the input x, and when s = 1, the output is equal to y. This is further displayed in the schematic of design below. Now in order for us to write the code for our design, we use the Boolean expression of a single-bit multiplexer described by the VHDL statement as: m...