Laboratory 1 ONLINE Explore Switches and Lights on DE10 Lite(1) PDF

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Laboratory 1 ONLINE Explore Switches and Lights on DE10 Lite(1)...

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NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York FALL, 2021

Component and Subsystem Design II CET 4805 SECTION D485 Meeting Day: Monday INSTRUCTOR: Prof.Pekcan STUDENT: Ahmed Imtiaz LAB Title: Tutorial 1: Schematic Design Implementing Boolean Equation using Altera’s Quartus software

Submission Date 09/20/2021

Objective: • Learn how to use the Quartus IIR V18.1 Premium Lite Edition software to create a schematic, Create waveforms, compile, and simulate a circuit.

Materials Used: Quartus IIR V18.1 Premium Lite Edition software by Intel Corporation

Lab Overview: This Lab is about to learn how to use Quartus II software and using this software Implemented a simple Boolean equation X=AB+CD.

Lab implementation: A. Create a Project:

1.Create a new project for circuit (Click on New Project Wizard)

2. Fill a name and top-level entity name for the project. You can pick any reasonable place for the work directory.

Click on Next. If the directory does not exist, you will see message. Click on Yes.

3.Select Project Type

Click on Next. 4. We don’t need to add any existing file to the Project for this Tutorial. Click on Next.

5. Family, Device and Board Settings If you downloaded and setup your software properly, you will see this screen:

and then click on Finish after seeing this Summary page:

Click ok , and place and2 (2 input AND gate) on the dotted Schematic (bdf workspace) screen. 3. Right click on the symbol and click on Properties. 4. Change the instance name to inst1. 5. Insert -> Symbol or2 (2 input OR gate) and assign the new instance name 6. Repeat the steps to implement X=AB + CD. The bdf workspace now has two AND and one OR gates with 4 input pins and 1 output pin. Then make circuit connections. (For the pins, use Insert/Symbol/pin/input and output, respectively.)

B. Compiling the project: 1. Choose Processing -> Start Compilation 2. If there is error, your compilation log screen will show 0 Errors

D. SIMULATION: Create a Vector Waveform File (vwf) to simulate the design

1. Choose File -> New -> Verification/Debugging Files -> University Program VWF -> OK

2. see a new window called Waveform window for the Simulation

5.Click on Edit-> Set End Time and set it to 20 us. 6. Click on View -> Fit in Window , to see the whole simulation range. 7. Next, set the inputs . Let us assign different clock frequencies as inputs to A, B , C and D. 8. Highlight the input A, choose Edit => Value => Overwrite Clock. Enter a period of 2 μs, then press Ok (or, right-click the blue-shaded are and then click Edit)

see a clock of 2us period is assigned to A. Then, do the similar clock assignments to the other inputs: Highlight the input B, choose Edit => Value => Overwrite Clock. Enter a period of 4μs, then press Ok Highlight the input C, choose Edit => Value => Overwrite Clock. Enter a period of 8μs, then press Ok Highlight the input D, choose Edit => Value => Overwrite Clock. Enter a period of 16 μs, then press Ok Choose File => Save

E. Perform a simulation of the output named X. 1. Choose Simulation => Run Functional Simulation 2. A “new” simulation window will pop up with your simulation results. See the following sample screen shot:

Conclusion and summary:

From this Lab we learned how to use Quartus II software and by using this software how to find the webform of logic circuit. This lab was easy to follow and easy to learn about all materials. From this lab knowledge will help us to solved more complex Logic gate solution in future Lab....