Lecture 1 PDF

Preview

Summary

Download Lecture 1 PDF

Description

Semiconductor Devices and Nanoelectronics Qiliang Li Dept. of Electrical and Computer Engineering George Mason University, Fairfax, VA [email protected]

Email: [email protected]

1

Content Outline • Semiconductor materials and the carriers in semiconductors; • Semiconductor fabrication and devices physics for pn junction, metal-semiconductor junction and MOS structure; • MOSFET, its basic circuits (inverter, NAND and NOR logic) and memory devices (Flash, SRAM, DRAM and other NVM) • Concepts in Nanoelectronics Email: [email protected]

2

What is semiconductors? • Their electrical conductivity is between that of metals (e.g., Al, Au, …) and insulators (e.g., SiO2, Al2O3 and HfO2); • Semiconductors are the foundation of modern electronic circuits • Important concepts: pn junction, transistor (BJT and MOSFET), solar cell, Light-emitting diode, digital and analog integrated circuits Email: [email protected]

3

The Common Semiconductors • Conventional semiconductors: Silicon (Si), germanium (Ge), GaAs, GaN, SiC … • One dimensional semiconductor: nanowires and nanotubes • Two-dimensional semiconductors, e.g., MoS2 • we are always looking for new functional semiconductor materials

Email: [email protected]

4

Chapter 1. Electrons and Holes in Semiconductors 1.1 Si Crystal Structure • Unit cell of Si is cubic • Each Si atom has 4 nearest neighbors 5.3 A Email: [email protected]

5

1.2 Bond Model of electrons and holes Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Si

Doped Si As: group V B: group III EION = 50 mV Very low

Intrinsic Si

Si

Si

Si

Si

Si

Si

Si

As

Si

Si

B

Si

Si

Si

Si

Si

Si

Si

Email: [email protected]

6

1.3 Energy Band Model

}

Empty upper bands

(conduction band)

3P 3S

(valence band)

} (a)

Filled lower bands

(b)

The highest filled band is the valence band The lowest empty band is the conduction band Email: [email protected]

7

1.3 Energy Band Model Conduction band

Ec

Band gap Eg Ev Valence band

 Energy band diagram shows the bottom edge of conduction band, Ec , and top edge of valence band, Ev .  Ec and Ev are separated by the band gap energy, Eg . Email: [email protected]

8

1.4 Energy Band structure Si band structure Indirect band gap 6 minimum at

Email: [email protected]

9

1.4 Energy Band structure Ge band structure Indirect band gap 8 minimum at

Email: [email protected]

10

1.4 Energy Band structure GaAs band structure Direct band gap

Email: [email protected]

11

1.5 Calculate the band structure Common methods: • Slater-Koster tight-binding method • Semi Empirical extended Huckel method (using Huckel molecular orbital theory) • Density functional theory (DFT) – LocalDensity Approximation (LDA) method • Density functional theory (DFT) – Generalized Gradient Approximations (GGA) method Email: [email protected]

12

1.5 Calculate the band structure Use MoS2 monolayer as example:

Email: [email protected]

13

1.5 Calculate the band structure MoS2 band structure calculated by using DFT-GGA method Direct band gap Eg = 1.79 eV Effective mass: ml = 0.59 m0 mt = 0.50 m0 mdos = (6)2/3(mlmtmt)1/3 = 1.75 m0

We used Virtual Nanolab ATK software to calculate it.

Welcome collaboration on the research! Email: [email protected]

14

Chapter 2. Device Fabrication and Physics 2.1 Device Fabrication Technology

2.1 Device Fabrication Technology VLSI (Very Large Scale Integration) ULSI (Ultra Large Scale Integration) GSI (Giga-Scale Integration) Variations of this versatile technology are used for flat-panel displays, micro-electromechanical systems (MEMS), and chips for DNA screening... Email: [email protected]

16

2.1 Device Fabrication Technology Arsenic implantation

(0)

P-Si

(1)

SiO2

(4) SiO2

Wafer

SiO2

Ion Implantation

P-Si

P-Si

Oxidation

(5)

SiO 2

SiO

(6)

Al SiO2

SiO2 N+

Mask

Al Sputtering

P

Positive resist SiO2

Lithography

Annealing & Diffusion

P

UV (2)

SiO2 N+

UV

P-Si Mask

(3)

Etching

SiO2

SiO2

(7)

Res is t

Al

P-Si

SiO2

N+

SiO 2

P

Lithography * An example from “Modern Semiconductor Devices for Integrated Circuits” (C. Hu) Email: [email protected]

17

2.1 Device Fabrication Technology Metal etching

(8)

Al SiO2

SiO2

(12)

N+

P

CVD (9) nitride deposition (10) Lithography and etching

Si3 N4 Al SiO2 N+

Si3 N4

P

Al

SiO 2

SiO 2

Au

N+

P

wire

Si3 N4 Al SiO 2

SiO 2

Si 3N 4

(13)

N+

(11)

SiO2

+

N

P

Photoresist

Au Plastic package

Si3 N4 Al SiO 2

Al

SiO2

P

Back Side milling

SiO 2

Back side metallization

metal leads

SiO 2 +

N

P

Dicing, wire bonding, and packaging

* An example from “Modern Semiconductor Devices for Integrated Circuits” (C. Hu) Email: [email protected]

18

2.2 pn Junction Electric Field Neutral Region

Depletion Layer

Neutral Region

N

P xnN

xpP

0

On the of the depletion layer, = –qNa dE dx

qNa s

qNd xP xnN

x

E( x )

–qNa

On the E( x)

0

x C1

s

E

xnN

qN a

xpP

x

Email: [email protected]

( xP

x)

s

, qN d

qN a

= qNd

( x - xN )

s

19

2.2 pn Junction Electric Field and potential

On the P-side,

E

V (x) xnN

xP

0

x

x )2

Arbitrarily choose the voltage at x = xP as V = 0.

V bi

xnN

qN a ( xP 2 s

xpP

x Ec

bi , built-in potential

Ef Ev

On the N-side, V ( x) D qN d ( x xN )2 2 s qN d 2 x x ( ) bi N 2 s

Email: [email protected]

20

2.2 pn Junction

Depletion layer width Neutral Region

Depletion Layer

Neutral Region

N –xnN

V is continuous at x

P

0 xP

If Na >> Nd , as in a

xN

Wdep

2

s bi

q

 1   Na

1   N d 

P+N junction,

2 s bi qN d

Wdep

xpP

0

|x P| |xN|N d

xN

N

a

0

What about a N+P junction?

Wdep

2

s

bi

qN where

1 N

Email: [email protected]

1 Nd

1 Na

1 lighter dopant density 21

2.2 pn Junction +

V

–

N

Reverse-Biased P

2 s(

Wdep bi

+ qV qV

Ec Efn

Efp Ev

1/C dep2

(b) reverse-biased 2

W dep

Cdep

2

A2

2 s

2

s

Reverse biased PN junction is a capacitor.

Ev

1

| Vr |)

qN

Ec q

bi

potential barrier qN

Cdep

A

s

Wdep

Capacitance data

2( bi V ) qN S A2

How to minimize the junction capacitance?

Slope = 2/qN s A2 Vr –

bi

Email: [email protected]

Increasing reverse bias

22

2.2 pn Junction - breakdown Peak electric field and breakdown voltage:

Ep

E(0)

 2qN (   s

1/ 2

bi

 | Vr |)  

VB

s Ecrit 2qN

2 bi

Impack ionization  avalanche breakdown

Tunneling Breaking

Ec

original electron

Efp Ev

Filled States -

Empty States Ec electron-hole pair generation

J Ge Ep

H/

εp

Ev

Ec Efn

6 Ecrit 10 V/cm

Basis for tunneling FET for smaller subthreshold swing Email: [email protected]

VB

1 N

1 Na

1 Nd 23

2.2 pn Junction – forward bias n (x P ) n ( x P ) n P 0 p (xN )

p(xN )

pN0

p ( x)

pN (eqV / kT 1)e 0

n ( x)

n P 0 ( eqV

/ kT

1) e

n P0 (e qV

kT

p N 0 (e qV x x N /L p

x xP / Ln

1) kT

1)

, x

xN

, x

xP

L: diffusion length ~ 10 um, depending on N

Total current

J pN ( xN ) J nP ( xP )

 Dp q  L p p N0 

q

 Dn nP0  ( eqV Ln 

J at all x

kT

1)

Minority carrier injection Email: [email protected]

24

2.2 pn Junction – Solar Cell

I sc

Voc * “Modern Semiconductor Devices for Integrated Circuits” (C. Hu) Email: [email protected]

AJ p (0)

AqLp G

kT 2 ln( p GN d / ni ) q 25

2.2 pn Junction –LED

Direct band gap Example: GaAs Direct recombination is efficient as k conservation is satisfied.

Indirect band gap Example: Si Direct recombination is rare as k conservation is not satisfied LED wavelength ( m) Email: [email protected]

1.24 photon energy

1.24 E g (eV ) 26

2.3 Metal-Semiconductor Junction

Two kinds of metal-semiconductor contacts: • Rectifying doped silicon

: metal on lightly I

V

Reverse bias

•Low-resistance

Forward bias

: metal on

heavily doped silicon Email: [email protected]

27

2.3 Metal-Semiconductor Junction Schottky Barrier Metal q

Depletion layer

Neutral region

• Schottky barrier height,

Bn

B,

Ec Ef

is a function of the metal material.

Ev

• B is the most important parameter. The sum of q Bn and q Bp is equal to Eg .

N-Si

Ec

P-Si Ef

q

Bp

Ev

Email: [email protected]

28

2.3 Metal-Semiconductor Junction Vacuum level, E0 Si

q

= 4.05 eV

M

q

Ec

Bn

+ Ef

Ev

A high density of energy states in the bandgap at the metal-semiconductor interface pins Ef to a narrow range and Bn is typically 0.4 to 0.9 V. Eg Bn + Bp

Silicide-Si contact:

Silicide ErSi1.7 HfSi MoSi2 ZrSi2 TiSi2 CoSi2 WSi2 NiSi2 Pd2Si PtSi 0.45 0.55 0.55 0.61 0.65 0.67 0.67 0.75 0.87 Bn (V) 0.28 0.55 0.49 0.45 0.45 0.43 0.43 0.35 0.23 Bp (V) * “Modern Semiconductor Devices for Integrated Circuits” (C. Hu) Email: [email protected]

29

2.4 Metal-Oxide-Semiconductor Capacitor Vg

Vg gate gate

metal

SiO2

SiO2 N+

Si body

N+

P-body

MOS transistor

MOS capacitor

Email: [email protected]

30

2.4 MOS – flat-band condition SiO2

0

=0.95 eV

Ec q

g

3.1 eV

3.1 eV

q s=

Si

Si

+ (Ec –Ef )

=4.05eV

Ec, Ef

Ec

qVfb

Ev N+ -poly-Si

E0 : Vacuum level E0 – Ef : Work function E0 – Ec : Electron affinity Si/SiO2 energy barrier

P-body

9 eV

4.8 eV

Ef Ev

The band is flat at the

V fb

g

.

s

Ev SiO2 Email: [email protected]

31

2.4 MOS – surface accumulation Make Vg < Vfb 3.1eV

Vg

Vox

Ec ,E f Ev

s

Vox

: surface potential, band bending

E0 qVg

: voltage across the oxide q

s

Ec Ef Ev

M

V fb

O

is negligible when the surface is in accumulation. s

S

Email: [email protected]

32

2.4 MOS – surface accumulation Vox

V g Vfb) qVox Ec q

gate qVg

-- -- -- -- -- -- --------

Wdep depletion

Ec, E f

depletion layer charge, Q dep

Ef Ev

---

++++++ SiO2

s

region

Ev

P-Si body

M

Vox

Qs Cox

V g V fb

s

Qdep

qN aWdep

C ox

Cox

Vox V fb

qN a 2

s

O

S

s

Cox

qN a 2 s

* “Modern Semiconductor Devices for Integrated Circuits” (C. Hu) Email: [email protected]

Cox

s

s

s 34

2.4 MOS – surface inversion Threshold of inversion: ns = Na , or

Ec

(Ec–Ef)surface= (Ef – Ev)bulk , or qVg =

 A=B, and C = D st

q

2 Eg

B

2

B

2

(E f

At threshold:

=

Ef Ev

B

Ec, Ef

kT  N a   ln q  ni  E v ) |bulk

Ei

A D

Ev

kT  N v   ln q  ni 

kT  N v  ln   q  N a 

V t V g at threshold Email: [email protected]

M

O

S

kT  N a   ln q  ni 

V fb

2

B

qNa 2 s 2 Cox

B

35

Vt (V), P+ gate/N-body

V t(V), N + gate/P-body

2.4 MOS – Threshold Voltage

Body Doping Density (cm-3 )

Vt

V fb

2

qN sub 2 s 2 B

Cox

B

+ for P-body, – for N-body

* “Modern Semiconductor Devices for Integrated Circuits” (C. Hu) Email: [email protected]

36

2.4 MOS – Capacitance vs. Voltage C

dQg dVg

dQs dVg

Qs accumulation depletion regime regime

inversion regime

C Cox

Vfb 0

Vg

Vt Qinv slope =

Cox

V V accumulation fb depletion t inversion

Email: [email protected]

Vg

37

2.4 MOS – Capacitance vs. Voltage C Cox

accumulation Vfb depletion

In the depletion regime:

1 C

1 C

1 C ox 1 Cox2

Vt inversion

Vg

1 C dep 2(Vg V fb ) qN a

Email: [email protected]

s

38

电子有足够时间response

Email: [email protected]

39

2.4 MOS: C-V Curve Fitting CVC is a open source software (by NCSU) for CV fitting • • • • • • • •

•

/* Lines with '/*' as first entry are ignored */ eoxr = 3.9 /* Relative dielectric constant for insulator */ 你用的材料的介电参 数，如果不是氧化硅的要改 esr = 11.8 /* Relative dielectric constant for semiconductor */ 衬底材料的介 电参数，如果不是硅的要改 ni = 1.44e10 /* Intrinsic carrier density */ 这是硅的intrinsic carrier density， 如果不是硅的要改 nc = 2.80e19 /* Conduction band density of states */这是硅的导带 carrier density，如果不是硅的要改 nv = 1.04e19 /* Valence band density of states */这是硅的价带 carrier density，如果 不是硅的要改 ego = 1.17 /* Extrapolated T=0 semiconductor band gap */这是硅的禁 带宽度（温度为0时的带宽） alf1 = 4.73e-4 /* Temperature corfficient of band gap -- form eg = ego - alf1*T^2/(T + to1) */这是温度对能带Eg的影响，材料不同而有所不同，不过，这是微调，在很多情 况下，不太重要。 to1 = 636. /* Coefficient for temperature dependancy of band gap */ 同上，你可以看到，硅和GaAs就有些不同。 Email: [email protected]

40

Chapter 3. Introduction of MOSFET and its applications The MOSFET (MOS Field-Effect Transistor) is the building block of Gb memory chips, GHz microprocessors, analog, and RF circuits. Match the following MOSFET characteristics with their applications: • small size • high speed • low power • high gain Email: [email protected]

41

Basic MOSFET structure and IV characteristics

Email: [email protected]

42

3.2 Complementary MOSFETs Technology

* “Modern Semiconductor Devices for Integrated Circuits” (C. Hu) Email: [email protected]

43

Static Complementary CMOS VDD In1 In2

PUN

PMOS only

InN F(In1,In2,…InN) In1 In2 InN

PDN NMOS only

PUN and PDN are dual logic networks Email: [email protected]

44

3.3 CMOS (Complementary MOS) Inverter Vd d PFET

Vin

S D

Vo ut

D S NFET 0V

C: capacitance (of interconnect, 0V etc.)

A CMOS inverter is made of a PFET NFET . Vout = ? if Vin = 0 V. Email: [email protected]

and a

45

Email: [email protected]

46

Inverter Speed – propagation delay Vdd

...........

To measure the speed V1

V2

V3

............ C

d

C

1 ( pull down delay 2 pull up delay)

V2

V dd

pull up delay 2

d

V3

CVdd 2 IonP

pull down delay

V1 0

CVdd 2 I onN

t d

: propagation delay Email: [email protected]
<...