Structure and Design Of Digital Systems - Lecture notes - L00 - Overview PDF

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LEC 0: Intro to Course & Comb Logic 18-240: Structure and Design of Digital Systems Don Thomas & Bill Nace! Spring 2015 © 2004 - 2015. All Rights Reserved. All work contained herein is copyrighted and used by permission of the authors. Contact [email protected] for permission or for more information.

Sanity Check... •

This is Carnegie Mellon University

- Department of Electrical & Computer Engineering - Spring 2015 Semester - 18-240 Structure and Design of Digital Systems ✦ 12 units ✦ 2 x 80 min lectures, plus... ✦ 1 x 3 hour lab, 1 x 50 min recitation ✦ Prerequisite: 18-100 for ECE students ✦ Corequisite: 21-127 (Concepts of Math)

•

If any of this is surprising or unexpected...

- ...we need to chat 18-240 L00 — 2

18-240: Where are we...? •

3 Handouts: Lecture Notes, Syllabus, Schedule

- Recitations start this week - No labs this week Week

Date

1

1/13

L0 Introduction, Comb. Logic

HH 1.1-1.3, 1.5

1/15

L1 Boolean Algebra

HH 2.1-2.4 LDVUS Backdrop, 1.1

1/16 2

HH 4.1 LDVUS 1.2 - 1.5

1/22

L3 Karnaugh Maps

HH 2.7

HW

No Lab

Lab 0

HW 0

Lab 1

HW 1

Lab 2A

HW 2

Lab

HW 3

Recitation

1/27

L4 Logic Minimization (Q-M Algorithm)

1/29

L5 Structured Logic Implementation

HH 2.8, 4.5

Recitation

2/3

L6 Synthesizable SystemVerilog

HH 4.2-4.3 LDVUS 2 - 2.3

2/5

L7 Numbers and Arithmetic

HH 1.4, 5.1-5.3

2/6

Lab

Recitation L2 Verilog HDL and Simulation

1/30 4

Reading

1/20

1/23 3

Lecture

Recitation

5

HH 1.7, 2.5-2.6

18-240 L00 — 3

18-240: Who are we…? Characters

Bill Nace Professor (Lectures, Labs, HW)

Don Thomas Professor (Lectures, Labs, HW)

Zara Collier Academic Support (Logistics)

Plus, a platoon of intelligent, energetic, kind, courteous, trustworthy,! dedicated, loyal, hard-working, hygienic, ECE-approved LAB TAs... 18-240 L00 — 4

18-240: What are we...? •

So, what is CompE...? Not unreasonable question...

- We have hard-core CompE ECE folks in here - ...and EE-leaning ECE folks - ...and CS folks (and double majors) - ...and several non-ECE/non-SCS folks as well Today’s Topic:

What is

CompE?

Kyle, I like totally hope he’s not going to do career counseling now...

18-240 L00 — 5

Computer System Abstractions Applications Compilers

18-240

OS Architecture (ISA) Microarchitecture Digital Design Circuits Devices/Physics

human interface prog. languages resource virtualization hw/sw interface datapath registers, ALU digital logic transistors, signals atoms, electrons

To use an abstraction properly you must understand the limits of the abstraction 18-240 L00 — 6

s of Digital System Design

(

e “system”

)

Note: I could have started with a very different, bigger system -- same breakdown …implemented as a set of components on a circuit board

on individual chips

…implemented as “SOC” system-on-chip complex integrated circuits

18-240 L00 — 7

A wide range of applications Leading-edge multi-core CPU

Embedded system

Computer Systems

ApplicationSpecific-IC (ASIC) — here a video processor 18-240 L00 — 8

Fundamental abstractions •

Combinational logic design

- What do you do when your circuit doesn’t fit

1/1

R A 00

into a nice 6-variable Kmap? Arithmetic circuits

0/1

0/1

•

Finite state machine

- State transition diagrams, state assignment,

B 01

0/1 Legend q1 q0 x/z

1/1

C 11

1/0

synchronous design style, Mealy/Moore timing and implementations

•

Register-Transfer Level systems

- Datapath components, control/status points, FSM control, register transfer level design

•

inAeq inAneq

inA == 0

Status Points

inA Control Points

Basic processor architecture and assembly language

- Micro-architecture, assembly language,

sum

+ addOut

ld_l cl_l ck

sum

reset_l

machine code

18-240 L00 — 9

Many aspects to the problem •

Design digital computation systems

- Computer architects (μProcessor designers) - Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) designers

- Embedded-system designers (software + hardware) - EE stuff: Digital electronic circuit designers (➙ 18-320) •

Develop tools for digital design

- Computer-Aided Design (CAD) software tools •

Design with computers

- Embedded systems - Networks, telecommunications, consumer parts, etc 18-240 L00 — 10

Why Do Computer Engineering? •

An active field that reinvents itself every few years

- Interesting, broad mix of hardware and software - Lots of products are (or require embedded) computers - Can’t design some software without knowing hardware •

Alternatives to Computer Engineering

18-240 L00 — 11

Course Schedule (Approx) •

Part 1: Combinational Logic

[Weeks 1 - 5]

- Boolean algebra, systematic representation & synthesis, SystemVerilog, higher-level parts, arithmetic circuits

- Exam 1 in week 6$ •

Part 2: Sequential Logic

[Weeks 6 - 10]

- Timing issues, Finite State Machines (FSMs) design, SystemVerilog representation, register-transfer design

- Exam 2 in week 12$ •

Part 3: Microprocessors

[Weeks 11-15]

- Computer architecture, assembly language programming, processor controlpath, datapath organization

•

Final exam

- Sometime during finals week -- we post when we know date 18-240 L00 — 12

18-240: About “Admin” Stuff (See Syllabus: Course Info)

•

2 Textbooks

- Digital Design and Computer Architecture by Harris & Harris (required)

- Logic Design and Verification Using SystemVerilog by Thomas (required)

•

Meetings

- 2 80-min Lectures -

✦ It’s considered “polite” to show up. (Smiling is good, too) 3-hour Lab (3 sections: Tue, Wed, Thurs nights) ✦ Done in groups of 2, except Lab0 ✦ Max 30 people per section due to equipment limitations

- 50-min Recitation (3 sections, all on Fri) ✦ You need to show up to your assigned section every time Unless you have MY written permission 18-240 L00 — 13

18-240: About “Admin” Stuff (See Syllabus: Course Info)

•

Grades

- 25% Homework: 12 HWs. Due Friday by 4:30pm ✦ Lowest 2 scores dropped

- 30% Labs: Done in groups of 2, except Lab0 - 25% Midterms: 2 exams x 12.5%. In class, closed book - 20% Final: Comprehensive, scheduled during Finals, closed book ✦ Aki rule: Exemption possible if grade >= 90% Date

4

9/16

L6 Structured Logic Implementation

HH 2.8, 4.5

9/18

L7 Numbers and Arithmetic

HH 1.4, 5.1-5.3

9/19 5

9/23 9/25

Lecture

HW from last week’s lectures

Week

ab 2A

HW 2

Lab 2B

HW 3

No Lab

HW 4

Recitation L8 Comb. Logic Wrap-up

HH 1.7, 2.5-2.6

Lab complete prior to Midterm

9/26 6

9/30 10/2 10/3

Midterm 1 L10 FSM Design

HH 3.4, 4.4

Recitation

18-240 L00 — 14

Academic Integrity • • •

Have it. Do it. Be it. Live it. (Understand it...) Don’t cheat Don’t copy other people’s stuff and hand it in

- You’re cheating yourself: (12/48) * $semester_of_tuition - Ok to give hints to other people about HW, but tell us who... - Most 18-240 problems come from “Over Collaboration” ✦ All work must be your own ➙ come from your brain ✦ If you copy from old answer keys … ✦ If you worked with someone else and don’t tell us … ✦ If you worked in a group and just wrote the group’s answer … ✦ … then you are cheating

18-240 L00 — 15

More “admin”: Lab partner / ECE acct •

Lab partners: Lab = 30 chairs & 15 benches

- We will assign you one (randomly) -- new one for each lab - Method to this (madness): forces you to learn how to talk to other tech folks (yes, just like the “real world”)

•

Manage group dynamics

- It’s your problem.... - ...unless you tell us$ early enough

•

ECE account:

- As a CMU’er, you already have an Andrew account - As an ECE’er, you also get an @ece.cmu.edu acct, needed to get at ECE Linux machines

- If you’re not ECE: send request to [email protected]

18-240 L00 — 16

Getting Answers to Questions •

Piazza.com Q&A website

- Keep an eye on your peers' questions - You can answer questions there as well - We tend to like students who participate •

Staff email list

- ece240-staff@ece.cmu.edu - Goes to all Professors and TAs •

Directly email Professor or TA

- Good for personal issues, stuff that pertains only to you •

Office Hours

- Profs: 2 hours per week - TAs: 1 hour per week (someone available just about every day) - Schedule is posted to Blackboard 18-240 L00 — 17

Current 18-240 Lab Equipment •

Computers

- PC’s on every lab bench - Linux, dual headed •

Hardware

- Altera Educational Boards — FPGA/CPLD - Implements designs with thousands of logic gates •

Software (CAD tools) on Linux

- SystemVerilog simulator (CVS) - Logic synthesis tools - Microprocessor simulator

18-240 L00 — 18

Labs: SystemVerilog to FPGA 1/1

R A 00

module FSM 0/1

(input logic

x, ck, r,

output logic z);

0/1 0/1

Legend q1 q0 x/z

1/0

B 01 1/1

LED outputs

C 11

enum {A, B, C=3} state;

always_ff @(posedge ck, negedge r) if (~r) state...