(T)EE2028 2010 Lecture 1 Intro and Concepts PDF

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Dr Henry Tan, ECE, NUS E-mail: [email protected][T]EE2028 MicrocontrollerProgramming & InterfacingLecture 1[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS 2Teaching Team Lecturers:  Part I*: Dr Henry Tan (μC Programming)  Part II : Dr Gu Jing (μC ...

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[T]EE2028 Microcontroller Programming & Interfacing Lecture 1 Dr Henry Tan, ECE, NUS E-mail: [email protected]

Teaching Team  Lecturers:  Part I*: Dr Henry Tan (μC Programming)  Part II : Dr Gu Jing (μC Interfacing: The Transition)  Part III: Dr Rajesh Panicker (μC Interfacing & Interrupts)

 Teaching/Lab Assistants:  Dr Ba Myint (Tutor & TA for Lab)  TBC (~8 Graduate Assistants) *Acknowledgement: The content of Part I is partly adopted from the original EE2028 material created by my predecessor, Assoc Prof Tham Chen Khong [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

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What you will learn in this module Develop an ARM embedded system using assembly language (asm) & C Interface with devices such as sensors & actuators using industry-standard protocols

[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

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Syllabus Week

Topics

1-3

I: Introduction & Microcontroller Programming    

4–6

Introduction to Microprocessors & ARM ARM Cortex-M4 (STM32L475) Overview Microprocessor Concepts ARM Instruction Set & Assembly Language

II: Interfacing – The Transition from CPU to System    

Advanced C Programming STM32L475 Board Familiarization Embedded System Development through C (CMSIS) General Purpose I/O (GPIO); Extended Int Event Ctrl’er (EXTI)

7 – 12 III: Interfacing & Interrupts

 Inter-Integrated Circuit (I2C) Protocol  Interrupts and Nested Vectored Interrupt Controller (NVIC)  Universal Asynchronous Receiver/Transmitter (UART) Protocol

[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

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Lab Sessions & Assignments 6+2 Lab Sessions

(@ Digital Electronics Lab E4-03-07)

    

Session #1: Familiarization with Development Environment (Week 3) Session #2: Assembly Language & C Programming (Week 5) Session #3: Assignment 1 Assessment (Week 6) Session #4: System Design & STM32L475 Familiarization (Week 7) Session #5: Interfacing to Sensors & Output Devices using GPIO & I2C (Week 8)  Session #6: Interrupt Handling & Event Detection (Week 10)  Session #7: Interfacing to External System using UART (Week 11)  Session #8: Assignment 2 Assessment (Week 13)

2 Assignments  Assignment 1: C & ARM Assembly Language (Weeks 3-6)  Assignment 2: ARM Embedded System Development (Weeks 7-13) [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

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Assessments Assignments (50%): During Lab Sessions #3 & #8 (i.e. Week 6 & Week 13) @ Digital Electronics Lab (E4-03-07) 30 mins per team of two (schedule to be announced)

Examination (50%): Wednesday 2 Dec 2020 9:00 am to 11:00 pm (120 mins) @ venue to be announced [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

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Books Due to the state-of-the-art nature of this module, there is no single recommended textbook.  Supplementary Reading:  Joseph Yiu, The Definitive Guide to the ARM Cortex-M3 & Cortex-M4 processors, Newnes, 2014 (eBook-Full Text Online, available at NUS libraries)  Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian: Computer Organization & Embedded Systems, 6th Edition, McGraw-Hill, 2012. ISBN 978-007-108900-5. Note: This book addresses the older ARM7TDMI (ARMv4T) & other processors, while this module focuses on ARMv7E-M architecture instead. There are some differences.  Yifeng Zhu, Embedded Systems with ARM Cortex-M Microcontrollers in Assembly Language & C, 2nd edition, E-Man Press LLC, 2015  ARM, ARM®v7-M Architecture Reference Manual (Chapters A4 & A7)  ST, RM0351 Reference Manual (for STM32L4x5)  ST, STM32L475xx Datasheet [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

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Learning Outcomes  Able to apply advanced C programming concepts such as structures & pointers  Able to apply knowledge of microprocessor concepts to program a microprocessor or microcontroller using C & assembly language to perform an engineering task  Able to use different addressing modes to efficiently access data in CPU registers & memory  Able to configure CPU interrupts with different priorities to reflect the importance of different events  Able to apply knowledge of computer interfacing protocols such as I2C & UART, & write C program statements to interface a microprocessor to other devices such as sensors and actuators  Able to specify the desired system behaviour of an application using diagrams like flowcharts  Able to develop a fairly complex embedded system application involving interfacing & interrupts, & verify how well it meets specifications & performs specified functions  Able to use an advanced Integrated Development Environment (IDE) to develop assembly language & C programs for embedded systems [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

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How to approach this module? Understand underlying design principles, concepts & protocols, both hardware & software aspects

Understand the ARM assembler code & main C libraries which implement the concepts & protocols Use these to create a useful embedded system & application! Work hard on the 2 Assignments: start early & make sure you complete each section by the stated time End-of-term Examination: prepare early [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

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Introduction to Microprocessors, ARM & ARM Cortex-M4 (STM32L475) [T]EE2028 Dr Henry Tan, ECE, NUS E-mail: [email protected]

Introduction to Microprocessors & ARM Objectives:  Understand the evolution of computing & the position of ARM Cortex-M4 (STM32L475) in the landscape  Differentiation between ARM processor & ARM-based MCUs  Introduction to STM32L475VG & its key features

Outline:  Short history of computing & ARM  ARM Cortex-M4 Processor vs Cortex-M4-Based STM32L475  STM32L475VG System-on-Chip (SoC) [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

Introduction

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The Evolution of Computing

Image source: https://image.slidesharecdn.com/lab1-computerintro1-141104102522-conversion-gate01/95/lab-1-computer-intro1-8-638.jpg [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

Introduction

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(Advanced RISC Machines)

Advanced RISC Machine (ARM)  Primary business – selling easily integratable IP cores, which allows licensees to create, manufacture & sell their own CPUs, μP, μC (MCUs) & SoCs based on the cores  ARM has since become the most popular embedded processing architecture in the world As of Feb 2020, 160 billion ARMs shipped ! Product Family

Designed For

Example Use Cases

Cortex-A

Open Application Platforms; High Performance; Power Efficiency

Mobile Devices, Set-top Boxes, for Full-Featured OSs

Cortex-R

Real-time System; Mission-Critical; High Processing Power & Reliability; Low Latency

Airbags/Braking Systems, HDD/SSD Controllers

Cortex-M Microcontroller Embedded System; Low Power Consumption; Low Cost [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

Introduction

IoT Wireless Sensor Nodes, 3D Printers, Home Appliances 15

ARM Architecture Evolution 1994

2001

2002

2004

& Cortex-M4 (v7E-M)

STM32L475

Note: First Cortex-M4 processor shipped in 2010 [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

Introduction

Cortex-M4 Main Strengths: • High-performance • Power-efficient • Low cost • Low interrupt latency • Ease-of-use • Ease-of-integration 16

ARM SoCs in Popular Devices Apple A13 Bionic SoC (2019)

 CPU: Hexa-core (ARM-based Custom CPU)  Instruction Set: compatible to ARMv8.4-A  In Apple iPhone 11, 11 Pro/Pro Max

Samsung Exynos 990 SoC (2019)  CPU: Octa-core (Custom + Cortex A76 & A55)  Instruction set: ARMv8.2-A  In Samsung Galaxy S20, S20+, Note20/Ultra/5G

Qualcomm Snapdragon 8cx SoC (2020)

 CPU: Octa-core (ARM Cortex-A76)  Instruction Set: ARMv8.2-A  In MS Surface Pro X, Samsung Galaxy Book S, Lenovo Flex 5G, Yoga 5G (NB: 64-bit Only Available From Around 2013)

[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

Introduction

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M4

(e.g. M4-based STM32L475)

M4

M4

M4 M4

M4 M4

M4 M4

(e.g. Atmel, NXP, Si Lab, STM, TI)

M4 © Dr Henry Tan, ECE NUS

M4

Introduction

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Cortex-M4-Based STM32L475 in STM32L475VG SoC:

[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

Introduction

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STM32L475VG SoC Block Diagram_1:

[T]EE2028 Part I: [T]EE2028 Part II & III: [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

Introduction

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STM32L475VG SoC Block Diagram_2:

[T]EE2028 Part I: [T]EE2028 Part II & III: [T]EE2028 Lecture © Dr Henry Tan, ECE NUS

Introduction

STM32L475 Introduction  Ultra-low-power ARM Cortex-M4 Core operates up to 80 MHz  100 pin packaging

 These pins may have up to 8 functions  Desired function is programmable

 1 MB Flash, 128 KB SRAM  Cortex-M4 processor (32-bit):    

32-bit word length 32-bit data path 32-bit register bank 32-bit memory interfaces

[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

Introduction

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Microprocessor Concepts [T]EE2028 Dr Henry Tan, ECE, NUS E-mail: [email protected]

Microprocessor Concepts  Objectives:  Understand functional units, memory organization & instruction execution in a computer

 Outline:    

1. Functional units within a computer 2. Processor components & their functions 3. Memory organization, addressing & operations 4. Instructions & sequencing • RISC vs CISC instruction sets • Instruction execution • Instruction sequencing: branching & looping, condition codes

[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

Overview

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1. Functional Units Processor

I/O

Memory Input

Output

Arithmetic & Logic Unit (ALU)

System Bus

Timing & Control Unit (CU)

Registers

[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

1. Functional Units

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Functional Units _Typical Examples Input:

 Keyboard, touchpad, mouse, microphone, camera, sensors, communication lines, the Internet

Output:  Displays, speakers, earbuds, printers

Memory:  Cache memory (holds sections/blocks) • an adjunct to the main memory, fabricated on the processor chip • much smaller & faster than the main & secondary memory • holds sections of the program & data currently being executed

 Main memory (holds pages) • Static RAM (SRAM), Dynamic RAM (DRAM)

 Secondary memory (holds files) • magnetic disks, optical disks, flash memory devices [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

1. Functional Units

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Memory

Processor-memory interface

PC

ALU

IR LR

CU

SP [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

1. Functional Units

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2. Processor Components  Arithmetic & Logic Unit (ALU) for performing arithmetic & logic operations, usually on word*-size data operands  Timing & Control Unit (CU) for fetching program instructions & data from memory, executing them one after another, & transferring the results back to memory  Registers (typically 16 or 32), small amounts of fast storage each of which holds one word* of data. Usually classified into general-purpose (e.g. R0-R15) & special-purpose: Program Counter (PC), Instruction Register# (IR), Link Register (LR) & Stack Pointer (SP) *architecture-dependent; #read-only [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

2. Processor Components

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The Registers  The General purpose registers hold data^ & addresses  The PC register holds the memory address of the current/next instruction  The IR holds the current instruction

 The LR stores the return address when a subroutine/function is called  The SP holds the memory address of the last (most recent) data in the stack memory ^ data or “instruction” [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

2. Processor Components

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3. Memory Organization  Memory consists of many millions of cells  Each cell holds a bit of information, 0 or 1  Information usually handled in larger units: words/bytes  A word is a group of n bits  a word length is usually between 16 to 64 bits

 The memory is thus a collection of consecutive words of the size specified by the word length Notes: In our 32-bit ARM context: - word=32 bits, halfword=16 bits. (both are architecture-dependent) - byte=8 bits (each byte is addressable in the memory) ; nibble=4 bits - hexadecimal: 0x0-0xF (4 bits) (0000 – 1111 in binary; 0-15 in decimal) [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

3. Memory Organization

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3.1 Word & Byte Encoding  Consider the common word length of 32 bits

 Such a word in memory may store:  a machine instruction for a program (or part of it, as each machine instruction may require more than one consecutive words for encoding)  or, data: • a 32-bit unsigned/signed integer (i.e. MSB b31 is the sign bit) or • four 8-bit bytes (e.g. ASCII character codes) [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

3. Memory Organization

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[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

3. Memory Organization

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3.2 Addresses for Memory Locations  To store or retrieve items of information, each memory location has a distinct address in the memory map  Numbers 0 to 2k  1 , (k = number of address bits), are used as addresses for successive locations in the memory  Hence, these 2k locations constitute the address space, i.e. the range of memory addresses available to programs  This 2k range is also referred to as memory size, e.g.:  If k  20  220 or 1M locations,  If k  32  232 or 4G locations (i.e. 4 billions bytes!) [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

3. Memory Organization

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Byte Addressability  Information is usually represented by words  But the word length may range from 16 to 64 bits  Byte size is always 8 bits  Impractical to assign an address to each bit  As such, memory is always byte-addressable, i.e. an address is assigned to each byte  If byte locations have addresses ending with 0x 0, 1, 2, 3, … , for a word length of 32 bits, the word locations will have addresses ending with 0x 0, 4, 8, C, … , since 4 bytes made up a 32-bit-word [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

3. Memory Organization

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0x….8040

0x8043

0x8042

0x8041

0x8040

0x….8044 0x….8048 Every byte is addressable by its own byte address.

Note: memory is quite often also shown with the lowest address at the bottom – Be Careful!

[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

3. Memory Organization

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Endianness  Describes the order in which a sequence of bytes are stored in computer memory; or more generally, the internal ordering of a sequence of bytes  BIG endian: places the most significant byte first (into the lowest address byte) & the least significant byte last  little endian: places the least significant byte first (into the lowest address byte) & the most significant byte last Notes: In our 32-bit ARM context: - Control accesses & Instruction fetches are always little endian - Data accesses can be big or little endian, depending on endianness setting [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

3. Memory Organization

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0x….8040

0x8043

0x8042

0x8041

0x8040

0x….8044 0x….8048

Endianness

0x8040

[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

3. Memory Organization

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3.3 Memory Operations  CU initiates transfer of both instructions & data between memory & the processor registers  (low-level) Read memory operation: contents at memory address location given by processor is retrieved  (low-level) Write memory operation: contents at given memory location is overwritten with given data [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

3. Memory Organization

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4. Instructions & Sequencing  Basic types of instructions a computer must support:  data transfers to & from the memory, e.g. load, store  arithmetic & logic operations on data, e.g. add, or  program sequencing & control, e.g. branch  input/output transfers, • but they are usually memory-mapped, hence, they can be considered to be the same as the first instruction type

[T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

4. Instructions & Sequencing

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4.1 RISC vs CISC Instruction Sets  Nature of instructions distinguishes computers Reduced Instruction Set Computers

vs

Complex Instruction Set Computers

RISC (e.g. ARM, Apple, Samsung)

CISC (e.g. Intel, AMD, Motorola)

Simple Instruction Type; Reduced Set (30-40)

Complex; Extended Set (100-200)

Fixed Instruction Length: One Word

Variable Instruction Length: Multi-Word

One Cycle/Instruction (Except Load & Store)

Multiple Cycles/Instruction (4-120)

Instructions Accessing Memory: Load & Store

Almost All Instructions From The Set

Arithmetic/Logic Operands Must Be In Registers

Allow Direct Memory Operations

Limited Addressing Mode

Compound Addressing Mode

Highly Pipelined – Pipelining Is Easy

Less Pipelined – Difficult

Software-Centric

Hardware-Centric; Complex Processor

RISC  simpler, faster, more power efficient, cheaper ! [T]EE2028 Lecture 1: Introduction & Microprocessor Concepts © Dr Henry Tan, ECE NUS

4. Instructions & Sequencing

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4.2 RISC Instruction Set (Load/Stor...