Tutorial 5 Computer Organization and Architecture with Answer (Memory System) PDF

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Tutorial work with answers on memory system ...

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Computer Organization and Architecture

Tutorial 5 : Memory System

1.

Memory word size = 32 bit, block size = 4K words a. Find memory capacity if total blocks = 512 blocks Memory capacity = no of blocks * block size * word size = 512 * 4x210 *32 = 67108864 bits = 226bits =64Mbits b. Find number of blocks if main memory capacity 8Mbit

memorycapacity

8x220

No of blocks= blocksize*wordsize 4x210x3264blocks

2.

Total blocks = 16K, block size = 128 words, memory word size = 64 bit, find memory capacity. Memory capacity = no of blocks * block size * word size = 16x210 * 128 *64 = 134217728 bits = 227 bits =128Mbits

3.

A block direct mapping cache has lines/slot that contains 4 words of data. The cache size is 64Kline and the main memory capacity is 16Mbytes. a. How many bits are used for required to access all addresses of a main memory address? 16Mbyte = 24 x 220 = 24 bits b. How many bits required to access individual for words in cache? 4 bytes = 22 = 2 bits c. How many bits required to access all for lines/slots in cache? 64Kline = 26x 210 = 16bits d. Draw the format for main memory address by specifying the size of tag, line/slot and word. Tag= 24-16-2 = 6bits ,line=16bits ,word = 2bits e. Given the following main memory address 3AFF80h, find the values for tag, line/slot and word field in hexadecimal.

Computer Organization and Architecture Tag

line

word

0011 10 10 1111 1111 1000 00 00

Tag = 00 1110 = 0Eh, Line = 10 1111 1111 1000 000 =BFE0h, word =00 = 0h

f. What is line size (cache word/cache block size)? = tag + (no of word per line * word size) = 6 +(4 * 8) = 38 bits for each line g. Given the following information, find the main memory address in hexadecimal. tag 3Fh

line/slot 9DA3h Tag

word 11 line

word 10 Data

word 00

word

11 1111 1001 1101 1010 0011 10

4.

word 01

= FE768Eh

A block direct mapping cache has lines/slot that contains 4 words of data. The cache size is 16Kline. Main memory contains 16K blocks of 128 byte each. a. What is the total capacity of main memory in Mbytes? 2Mbytes b. How many bits are used for main memory address? 21bits c. How many bits for words in cache? 2bits d. How many bits for lines/slots in cache? 16K = 24x210 =14bits e. Draw the format for main memory address by specifying the size of tag, line/slot and word.

Tag : 5 bits

Line: 14 bits

Word :2 bits

f. Given the following main memory address AFF80h, find the values for tag, line/slot and word field in hexadecimal. Tag

line

word

1 1010 1111 1111 1000 0000 -- tag =0A, line = 3FE0, word = 0

g. What is line size (cache word/cache block size)? = tag + (no of word per line * word size)

Computer Organization and Architecture = 5 +(4 * 8) = 37 bits for each line

h. Given the following information, find the main memory address in hexadecimal. Tag

line

word

1 1111 00 1101 1010 0011 00

tag 1Fh

5.

line/slot DA3h

word 11

= 1F368Ch

word 10

word 01

word 00 Data

An associative cache has tags that contain 4 words of data. The cache size is 16Kline. Main memory capacity is 16Mbyte.

Computer Organization and Architecture

a. How many bits are used for main memory address? 16M = 24x220 =24 bits b. How many bits for words in cache? 4 = 22 = 2bits c. How many bits for tag in cache? For associative: tag = 24-2 = 22 bits d. Draw the format for main memory address by specifying the size of tag and word. Associative has only 2 field : tag = 22 bits and word = 2 bits e. Given the following main memory address ABCDEFh, find the values for tag and word field in hexadecimal. Tag

word 1010 1011 1100 1101 1110 11

11

f. What is line size (cache word/cache block size)? = tag + (no of word per line * word size) = 22 +(4 * 8) = 54 bits for each line

g. Given the following main memory address 777777h, find the values for tag and word field in hexadecimal. Tag

word

Computer Organization and Architecture 0111 0111 0111 0111 0111 01 11 h. Given the following information, find the main memory address in hexadecimal. tag

word 11

word 10

word 01

word 00

23341Fh

Data

10 0011 0011 0100 0001 1111 00 = 8CD07Ch

11.

A set associative cache size of 16Kline divided into 2-line sets (2-way) with block a line of of 4 words. Main memory capacity is 32Mbyte. a. How many bits are used for main memory address? 25 bits b. How many modules (sets) in cache? Set = 16K/2 = 8K c. How many bits for set numbers? 13 bits d. How many bits for block words? 2 bits e. Show the format of main memory addresses with tag, set and word bits. Tag: 25-13-2 =10bits, set- 13 bits, word 2 bits f. What is cache address (in hexadecimal) for the following main memory address 133AC0Bh?

01 0011 0011 1010 1100 0000 1011 -- 2B02h g. What is line size (cache word/cache block size)? = tag + (no of word per line * word size) = 10 +(4 * 8) = 42 bits for each line

h. What is main memory address (in hexadecimal) for the following cache data? Tag 34Ah

Set 1B5Ch

Tag,set,word

10bit

word 11

13 bits

word 10

word 01 Data

2 bits

= 11 1000 1010 1 1101 0101 1100 01 – group 4bits from left : the address – 1C57571h

word 00

Computer Organization and Architecture 12.

A set associative cache size of 64Kline divided into 4-line sets (4-way) with block of 4 words. Main memory capacity is 64Mbyte. a. How many bits are used for main memory address? 64M = 26x220 =26 bits

b. How many modules (set) in cache? 4 c. How many bits for set numbers? =16K = 24x210 = 14 bits d. How many bits for block words? = 4 = 22 = 2bits e. Show the format of main memory addresses with tag, set and word bits. Tag = 26-14-2=10 bits, set =14 bits,word=2 bits f. What is cache address (in hexadecimal) for the following main memory address 377AC01h?

11 0111 0111 1010 1100 0000 0001 = 2B00h g. What is line size (cache word/cache block size)? = tag + (no of word per line * word size) = 10 +(4 * 8) = 42 bits for each line h. What is main memory address (in hexadecimal) for the following cache data? Tag 34Ah

Set 3B5Ch

word 11 Data

word 10

word 01

word 00

11 0100 1010 11 1101 0101 1100 11 = 34AF573h

13.

Consider a 32-bit microprocessor that has an on-chip 16KByte four-way setassociative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?

32 microprocessor – address bits =32bits

Computer Organization and Architecture

Set = 12bits Word = 4 = 2bits

Tag = 32-12-2 = 18 bits, set = 12 bits,word = 2 bits

Address ABCDE8F8 = 1010 1011 1100 1101 1110 1000 1111 1000 = set address A3Eh

14.

The cache hit ratio is 95% (0.95) and the hit time is 1 cycle, but the miss penalty is 10 times slower than hit time. Given each cycle is 0.05 milliseconds. Find AMAT cycles and seconds. AMAT = Hit time + (Miss rate x Miss penalty) = 1+ 0.05*10 = 1.5 cycles AMAT = 1.5 cycles = 1.5 x 0.05 = 0.075 miliseconds

Memory Interleaving Example (a). Given a memory address 298h (10 bits) with 4 memory banks. Draw and determine the memory bank/module address (LOI) and the address of the word in the bank/module.

•

Total number of memory banks = 4 = 22 = 2 bits (There are 4 memory banks/modules, 22, thus 2 bit for the banks/modules address

•

LOI format Word in bank (8 bits)

Bank address (2 bits)

•

Memory bank capacity = 28 = 256 (8 bits for word in bank)

•

Memory capacity = 210 = 1 Kwords

Memory address = 298h = 1010 0110 00 Memory bank/module address = 00 Address of the word in the bank/module = 1010 0110 = A6h

Computer Organization and Architecture

Draw and label sequence of address for first and last module/bank using LOI. 1111 1111 00b

1111 1111 11b

3FCh 3FFh

1020

1021

1022

M3 (11)1023

0A6h

M0 (00)

M1 (01)

M2 (10)

0

1

2

000h 003h

3

Since these are high order bits, therefore its called HOI

0FF h

000h

1111 1111

0000000001 0000000000

011111 1111 255

M0 0

101111 1111 511

M1

0100000001 0100000000 256

767

M2 1000000001 1000000000

512

111111 111 1023

3FF h

M3 1100000001 1100000000 768

300h

These bits are same in all 4

0000 0000 11b 0000 0000 00b 2. Given memory capacity 1K with the memory bank/module size 256 word. Draw the modular memory for high order interleaving (HOI). •

Memory capacity = 1Kwords = 210 = 10 bits for main memory address

•

Module/bank size(capacity) = 256 = 28 = 8 bits for word in bank/module

•

Total number of bank/module = memory capacity/module(bank) size = 210 /28 = 4 module/bank

•

There are 4 memory banks/modules, 22, thus 2 bit for the banks/modules address modules....