Tutorial 7 - Sequential Circuits - Flipflops and Memory PDF

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In-depth notes and tasks relating to Decoder Circuits on Sequential Circuits...

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55-4794 Computer Systems and Architecture

Tutorial 5

Sequential Circuits - Memory In this tutorial you will explore circuits – generically called latches, or flip-flops - that allow a ‘state’ to be stored. This makes sequential circuits different to combinatorial circuits which have no storage capability. Usually these sequential circuits are used as the building blocks for the memory components of a computer system, such as processor registers, cache memories, input/output buffers, and other special purpose memories, as well as for dedicated circuits such as counters. The R-S Latch This is the basic circuit we shall consider - you should become familiar with its form and function as it is the basis for the variants discussed later in this tutorial. You have seen this circuit in the lecture; remember that S means Set (to 1) and R means Reset (to 0), and that Q is the output of interest - Q is simply the inverted form of Q and is provided for convenience:

S

Q

This may also be drawn as: Q S Q R

Q R

- but this makes the variants coming later less easy to draw so we will use the first form. Notice the feedback loop from the outputs. Either way the function of this circuit is defined in the truth table as: Whilst both R = 0 and S = 0 the output Q 'remembers' its current state - in other words, the flip-flop is acting as a 1-bit memory! Other circuits can safely 'read', or use, the Q output safe in the knowledge that it won't be changing - that is, it's stable.

R 0 0 1 1

S 0 1 0 1

Q Q' 1 0 Not defined!

This function can also be expressed in conventional boolean algebra as: Q  S  Q'

Q' and

Q'

represent the present state, or outputs, of the flip-flop.

Q R  Q '

So, if Q' = 0 (thus Q' = 1) and we set R = 0 and S = 1 we can follow the changes to the flip-flop - as it’s S which is set to 1 we’ll use that to find Q first, as follows: Q S  Q' Q 1  0  0  Q' and

currently after

R 0

S 1

Q' 0

Q 1

Q R  Q' Q 0  0 1

This is correct as setting S = 1 should set the output Q to 1, as it does here. If we do this again but this time calculate Q first we find a temporary instability in the outputs:

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Q R  Q' Q 0  1  0  Q'

Wait a moment! Q and Q are both 0, - this represents a temporary unstable condition.

and Q S  Q'

Continue to use the new Q' to re-calculate Q.

Q 1  0  0  Q' Q 0  0 1  Q' Q 1  1  0  Q'

Now that Q and Q are 1 and 0 respectively the flipflop can be considered stable.

The flip-flop 'settles down' very quickly to its sta Check this be re-calculating Q , - it stays at 0, good! in the circuit. It would be unrealistic to expect bo time and speed (why?) so a little temporary inst Task 1. Repeat the process shown above with Q' = 1 (thus Q' = 0) and with R = 1 and S = 0. As it's R that’s set to 1 the result should be that the output of the latch is reset to 0, i.e. Q = 0 should result.

R

S

Q'

1

0

1

Q ?

(If necessary, see the last page for the solution to this.) Task 2. Again, repeat the process shown above in order to show that setting both R and S back to 0 does not change the output Q = 0 from task 1.

R

S

Q'

0

0

0

Q ?

Task 3. Using the Logic Trainers, build an R-S Latch and ensure that you understand its operation. In particular, you should be able to demonstrate that setting R = S = 1 produces unpredictable outputs on Q (the output LED representing Q may turn on or off depending on how you flick the switches being used for R and S). Note: it might be less confusing if you do not connect Q to an LED, so that you only see Q. Alternatively, use a felt-tip pen to label the switches and LEDs.

The Clocked R-S Latch (or Flip-flop) Using a clocked latch allows the synchronisation of several latches at once. For example, 16 latches can be used to build a 16-bit register such as those used by a Pentium processor - each of these sixteen latches must be set, reset or read by other circuits at the same time otherwise chaos will reign in the system! A system clock is a regular electrical pulse on a wire, with, for example, 0 volts representing logic 0 and often 5 volts representing logic 1 levels. The clock can be visualised as a roughly ‘square’ wave pattern with a rising (or leading) edge and a falling (or trailing) edge: level

1

1

1

Clock signal 0

level

1

1

1

a clock cycle

0

0

0

0

0

time Falling or Trailing Risingcycle, or Leading edge The time a clock takes to go from level 0 to level 1 back to leveledge 0 again is one clock and the number of times this occurs per second is the clock frequency, often given as hertz (Hz) - see info box below. A processor quoted as being a 1.6GHz device has a clock driving it that has 1.6 x10 9 (that's a billion) clock cycles per second - making each clock cycle 62.5 nano seconds (nS) long! That's quick.

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Clock Rate (source: http://en.wikipedia.org/wiki/Clock_rate, but independently checked!) The clock rate of a CPU is normally determined by the frequency of an oscillator crystal. The first commercial PC, the Altair (by MITS), used an Intel 8080 CPU with a clock rate of 2 MHz. The original IBM PC (c. 1981) had a clock rate of 4.77 MHz (4,770,000 cycles/second). In 1995, Intel's Pentium chip ran at 100 MHz (100 million cycles/second), and in 2002, an Intel Pentium 4 model was introduced as the first CPU with a clock rate of 3 GHz (three billion cycles/second). The clock rate of a computer is only useful for providing comparisons between computer chips in the same processor family. An IBM PC with an Intel 486 CPU running at 50 MHz will be about twice as fast as one with the same CPU, memory and display running at 25 MHz. However, there are many other factors to consider when comparing the speeds of entire computers, like the clock rate of the computer's front side bus, the clock rate of the RAM, the width in bits of the CPU's bus and the amount of Level 1, Level 2 and Level 3 cache. Clock rates should not be used when comparing different computers or different processor families. Rather, some software benchmark should be used. Clock rates can be very misleading since the amount of work different computer chips can do in one cycle varies. For example, RISC CPUs tend to have simpler instructions than CISC CPUs (but higher clock rates), and superscalar processors can execute more than one instruction per cycle.

The clocked R-S flip-flop circuit is a level-triggered device - that is, it operates when the clock is at one of its two levels (and thus doesn't operate during the rising and falling edges). Consider the addition of the AND gates to the basic R-S latch (in the dotted box) as shown below:

S

Q

Clock Q R

In this circuit the two AND gates prevent the R=1 or S=1 input from passing through to the latch when the clock input is 0. Only when the clock input is at level 1 will the AND gates allow through a 1 from the R or S inputs. In this respect these do indeed act like real ‘gates’. Task 4 Complete the truth table overleaf for the clocked R-S flip-flop circuit, then add the necessary parts to your R-S flip-flop circuit on the breadboard from Task 3 to make it a clocked R-S, and confirm your table. Use a switch for the clock input and leave it in the 0 position initially (you may want to experiment with the 'clock' generator on the boards, but do not use them for this circuit - they run too quickly to see what's going on. Your manual clock switch will be running very slowly as you will be causing it to go from 0 to 1 and back again, and very asynchronously!) Notice how any changes to your R or S switches have no effect on the flip flop output until you change the clock to 1. This is sometimes termed 'clocking' in the input, or sometimes 'strobing'. As long as the clock remains at 1 the R and S inputs will affect the flip-flop as normal (but note that R=S=Clock=1 is still not allowed). In other words the flip-flop is transparent. When the clock is at 0 the flip-flop output Q (or 'state') is considered stable (and is available to be read by other circuits).

3

R

S

Clock

Q

0

0

0

Q'

0

1

0

?

1

0

0

?

1

1

0

0

0

1

0

1

1

?

1

0

1

?

1

1

1

?

?

… bit of a trick question! When the clock is low (equal to level 0, or false) the AND gates prevent the R and S signals getting to the flip-flop. So, will they have any effect on the output Q?

Q'

Note: frequently a specific control input other than a clock is used to synchronise devices in a real computer system. These are often called Enable inputs, because they enable the flip-flop or other component to operate (without the enable signal they remain ‘dormant’). In terms of logic they have the same effect as the clock input on the flip-flop, but enable signals are used for asynchronous activity – that is, events that may occur at irregular times, such as the use of a keyboard, rather than with the regular (synchronous) system clock.

The D-Type Flip-flop A development of this circuit that avoids the R=S=1 problem is the D-type Flip-flop. This is in fact simply a clocked R-S flip-flop except that there’s just one input, called D (for ‘Data’) where S=D and R D as shown below: This was S before

D Q

Clock Q

This was R before

Here, D simply represents the value you wish to store in the flip-flop when the clock is high (= 1), that is, Q=1 if D=1 and Q=0 if D=0. The difference now is that the clock plays a pivotal role, as the usual ‘stable’ condition of R=0 and S=0 will not (can not) occur. This means that the output of the D-type flip-flop must only ever be used (‘read’) when the clock is low (=0) as it cannot be changed by input D during that part of the clock cycle. Whilst the clock is high (=1) the output Q will simply equal the value on the D input (0

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or 1) - that is, the latch is again transparent when the clock is high. As D may change whilst the clock is high the Q output cannot sensibly be used during that part of the clock period.

Task 5 Alter your clocked R-S circuit to make it a D-type flip-flop. Check that it operates as expected (the truth table is given below). Notice that it’s level-triggered, as before. D 0 1 0 1

Clock 0 0 1 1

Q Q' Q' 0 1

Task 6 There are some ready-made D-type flip-flops available with the Logic Trainers. Using one of these, show that rather than being level-triggered these integrated circuits are actually edgetriggered and experiment with the inputs to find out whether the rising edge (clock 0>>1 transition) or falling edge (clock 1>>0 transition) is being used.



Clock

G ENABLE



D

Q

Q





Connect the lower left D-type flip flop as shown in this enlarged diagram taken from the chip carrier. The numbers refer to the carrier legs, 1 is the lower left corner.



NOTE: You will have to connect the ENABLE input of these D-types to a switch and ensure that it’s set to 0, otherwise this chip will not work. This method of enabling a chip - often called the chip enable (CE), or chip select (CS) input – is very common, and is used when one of several components (such as RAM memory chips) is being ‘addressed’ and the others must be ‘disabled’ to prevent conflicts.

5

If the clock is already at 1 when you change the D input you will have to switch the clock to 0 and then back up to 1 (in order to generate the rising edge) – you should have already deduced that these circuits use the rising edge of the clock! Note that the Q output no longer follows the D input even when the clock remains at 1 – this allows better synchronisation of multiple devices. In other words, the output Q could be used ('read') by subsequent circuits whilst the clock is high or low, they just have to avoid the rising edge part of the clock cycle.

D

Clock

Q

0

0

Q'

1

0

Q'

0

0

1

1

Note how the truth table looks somewhat different for these edge-triggered devices, with a symbol representing the clock edge being used to trigger the device:

6

7

The J-K Flip-flop Another variation on the basic clocked R-S is the J-K flip-flop (where J S and KR). This is a ‘value-added’ flip-flop in that it has inputs that explicitly Preset and Clear the Q output to 1 or 0 respectively, but also has the useful feature that the J=K=1 input state is valid (remember that the original R=S=1 is invalid) and that this has the effect of inverting the previous value of Q (i.e. Q' becomes Q' ). Task 7 Using the available integrated circuit chips for the J-K flip-flops prove that J=K=1 inverts the previous value of Q by wiring one up and experimenting with it. Remember that by simply leaving the J and K inputs unconnected they will default to logic 1 anyway (see Tutorial 2). What part of the clock cycle triggers this flip-flop (experiment to find out then check with the answer at the end of this tutorial sheet)?

The eponymous Jack Kilby, 1924-2005.

Task 8 Build a 4-bit J-K flip-flop shift register as seen in the lecture and reproduced below. Show that data can be loaded into such a 4 bit register in serial, with the clock input determining when the next bit is stored (compare this with the transmission of bits from a serial mouse, for example). Connect each of the Q outputs from the four J-K’s to a separate LED so that you can follow the bit pattern as it shifts along the register. To load this register in serial you need to set the first bit up on the switch connected to the first J-K input and then ‘clock’ it in. Change the switch for the next bit to be loaded and clock that one in. You should see the first bit move into the second J-K and the second appear in the first J-K. Repeat this, observing the value displayed on the LEDs, until you have stored four bits of your choosing in the register. By setting the input switch to zero you can now also show how a register value can be divided by two with each subsequent clock ‘tick’ (shift right = divide by 2). Register data when clocked in shows on LEDs and 7 segment display

Q3

J Clock

Q

J Clock

Q

K

Q1

Q2

J Clock

Q

J Clock

Q

K

Q

K

Q

Q0

Q Q

K

Clock

Data In (via a single switch connected to first J input)

Task 9 Build the four-stage ripple counter shown below. Connect the left hand clock input to the orange toggle switch to the left of the usual switches on the Logic Trainer, and connect the four Q outputs to the 7-segment decoder in addition to the LEDs (those marked A B C and D). Q3 J Clock

Q

K

Q

Q2

J Clock K

Q Q

Q0

Q1 J Clock K

Q Q

J Clock K

Q Q

Clock input (use the orange toggle switch on the trainer) 8

You can observe the counter incrementing with each press of the toggle switch. What happens when it gets to F? Notice how the Q output feeds the clock input of the following flip-flop. Clever, eh?!

Task 9a Alter the ripple counter so that another LED lights up when the counter reaches the value 5 (i.e. when the Q outputs show 01012). You will need to add the equivalent of a four input AND gate and two inverters to do this. Draw up the necessary extra circuit on paper first. Counter circuits are essential elements in a computer system; for example, how would the previous shift register circuit 'know' when to stop shifting bits in? Answer: when some counter circuit reaches the value 4 and produces a signal to stop the shifting (it's beyond the scope of this tutorial to explain how this happens in detail!).

Task 10 Build a 4-bit parallel register from D-type flip-flops as seen in the lecture notes (and reproduced below), connecting each D input to a separate switch and each Q output to a separate LED (you may also connect these to the inputs A,B,C,D of the 7-segment decoder too). Only one clock input switch is required and this should be connected (or propagated) to each of the four Dtypes. Show that a 4-bit value set up on the switches are loaded all at once (i.e. synchronised and in parallel) when the clock triggers them. Notice that there are four D-type flip-flops available on each chip carrier so you only need one to build this.

Bit pattern clocked into register shows on LEDs Q3 Q2 Q

D Clock

D

Q

D

Q1

Q0

Q

D

Clock

Clock

Q

Clock

Clock

D3

D2 4 bit parallel data set up on switches

D1

D0

9

Answer to Task 1

Doing Q first gives temporary instability: Q S  Q'

Q R  Q'

Q  0  1  0 Q'

Q 1  0  0 Q'

Q R  Q

Q S  Q'

Q 1  0  0 Q'

Q 0  0 1 Q'

This is stable immediately.

Q 0  0 1 Q'

Problem! Both outputs = 0, this is impossible! Deep breath, and keep going!

Q 1  1  0 Q'

Ah, OK now!

Answer to Task 7 J-K flip flops use the falling edge of the clock cycle.

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Addendum - The D-Type Flip-Flop

Internal workings of the IC version of the Edge-triggered D-type Flip-flop A positive-edge-triggered (rising edge, 0>>1) D-type flip-flop is built internally from linked D-type and R-S flip-flops, as follows: master: D-type

D

slave: R-S

D

Q

Clock

R Clock

Q

S

Q

The effect of these two extremes is that when the clock is = 0 the D input does not affect the final Q output, but does get into the master flip-flop.

Clock

Falling edge

When clock = 0 the master flip-flop (a D-type) is open to changes in the D input (because the inverter makes the clock input = 1), BUT its Q output (the middle one in the diagram) isn't seen by the slave R-S flip-flop due to the clock being = 0 there. So the final Q (on the right) is stable (unchanging) even though the D input may be changing.

Q

Rising edge

When clock = 1 the master flip-flop is closed to changes in the D input (because the inverter makes its clock input = 0), BUT its previously set Q output is finally passed onto the slave flipflop's S input (because the clock is = 1 t...