Very large scale integration Multiple choice questions PDF

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Very large scale integration Multiple choice important for tutorial and for practice purpose used for scoring maximum marks with ease...

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Long form of VHDL A. Very High speed Horizontal Description Language B. Very High Super Hardware Description Language C. Very High Speed Hardware Description Language D. Very Large Scale High spread Hardware Description language ANSWER:c which is data object A. std_logic B. constant C. boolean D. INTEGER ANSWER:B In process all statements are ________________execute. A. parallel B. random C. sequential D. concurrent ANSWER:C UNIT1-4 which statement is true A. procedure return many values B. package store in STD_LOGIC library C. function return maximum values D. case statement use in structural modeling ANSWER:A UNIT1-5 mealy machine means A. output depends on present state only B. output depends on clock signal only C. output depends on input as well as present state D. none of above ANSWER:C UNIT1-6 which statement is nonsynthesizable A. assert statement B. std_logic_vector data type C. case statement D. with select statement ANSWER:A UNIT1-7 variable declare A. In entity

B. in process C. after architecture program D. none of above ANSWER:B UNIT1-8 _______is data type in vhdl A. signal B. variable C. array D. file ANSWER:C UNIT1-9 ________________is nonsynthesizable statement A. interger data type in entity B. for loop statement in vhdl C. structural modeling style in VHDL D. variable data object in VHDL ANSWER:A UNIT1-10 Which is encoding technique of FSM A. moore B. mealy C. one hot D. excess-code ANSWER:C set-2 Which among the following is pre-defined in the standard package as one-dimensional array type comprising each element of BIT type A. Bit type B. Bit_vector type C. Boolean type D. All of the above ANS:B Which data type in VHDL is non synthesizable & allows the designer to model the objects of dynamic nature? A. Scalar B. Access C. Composite D. File ANS:B

In VHDL, which object/s is/are used to connect entities together for the model formation A. Constant B. Variable C. Signal D. All of the above ANS:C In Net-list language, the net-list is generated _______synthesizing VHDL code. A. Before B. At the time of (during) C. After D. None of the above ANS:C Among the VHDL features, which language statements are executed at the same time in parallel flow A. Concurrent B. Sequential C. Net-list D. Test-bench ANS:A In a VHDL program, the architecture can have more than one entity. A. True B. False ANS:B Which of the following describes the structure of a VHDL code correctly A. Library Declaration; Configuration; Entity Declaration; Architecture Declaration B. Library Declaration; Entity Declaration; Configuration; Architecture Declaration C. Library Declaration; Configuration; Architecture Declaration; Entity Declaration D. Library Declaration; Entity Declaration; Architecture Declaration; Configurations ANS:D Multiple processes in a VHDL code are executed ______. A. Sequentially B. Concurrently C. Based on the order of elements in the sensitivity list ANS:B _______ is the process of converting design information to a set of logic equations using EDA tools. A. Simulation B. Optimization

C. Synthesis D. Verification ANS:C The statements inside a VHDL process are __________. A. Primitive B. Sequential C. Concurrent D. Sequential or concurrent ANS:B set-3 Which of the following VHDL design units contain the description of the circuit A. Configurations B. Architecture C. Library D. Entity ANS:B Total number of inputs in a half adder is __________ A. 2 B. 3 C. 4 D. 1 ANS:A Which among the following is a process of transforming design entry information of the circuit into a set of logic equations A. Simulation B. Optimization C. Synthesis D. Verification ANS:C In Net-list language, the net-list is generated _______synthesizing VHDL code. A. Before B. At the time of (during) C. After D. None of the above ANS:C Which among the following is an output generated by synthesis process A. Attributes & Library

B. RTL VHDL description C. Circuit constraints D. Gate-level net list ANS:D Which among the following is/are regarded as the function/s of translation step in synthesis process A. Conversion of RTL description to boolean unoptimized description B. Conversion of an unoptimized to optimized boolean description C. Conversion of unoptimized boolean description to PLA format D. All of the above ANS:A How much logics contents in std_logic data type A. 2 B. 9 C. 8 D. 16 ANS:B Which data type is non synthesizable A. std_logic B. std_logic_vector C. integer D. bit ANS:C How much input bit content of std_logic_vector(5 downto 0) A. 5 B. 2 C. 6 D. 4 ANS:C What is std_logic_1164 in vhdl programing A. Package B. Data type C. Data object D. synthesizer ANS:A

Procedures are useful when _________ a) Functions are not synthesizable b) Signals are needed to be declare c) Multiple values are needed as a result d) Architecture can’t contain some statement ans:c Procedure doesn’t have a return type. a) True b) False ans:a A procedure can’t contain a _______ statement. a) WAIT b) IF c) RETURN d) CASE ans:c . A function is a ________ code. a) Concurrent b) Sequential c) Concurrent as well as sequential d) Process oriented ANS:B How many return arguments can be there in the function? a) 1 b) 2 c) 3 d) 4 ANS:A A function call can be a concurrent as well as a sequential statement. a) True b) False ANS;A In VHDL, which object/s is/are used to connect entities together for the model formation? a. Constant b. Variable

c. Signal d. All of the above ANS:C Hold time is defined as the time required for the data to ________ after the triggering edge of clock. a. Increase b. Decrease c. Remain stable d. All of the above ANS:C Which of the following is true about packages? a) Package is collection of libraries b) Library is collection of packages c) Package is collection of entities d) Entity is collection of packages ANS:B A package may consist of _________ design units. a) 2 b) 3 c) 4 d) 5 ANS:A Any item declared in a package declaration section are visible to _______ a) Every design unit b) Package body only c) Library containing that package d) Design unit that USE the package ANS:D If a user wants to include his/her own package in the body, which library he/she must use? a) STD b) IEEE c) WORK d) STD_LOGIC ANS:C

It is possible to modify the STD_LOGIC_1164 package of IEEE library.

a) True b) False ANS:B Which of the following is the correct use of the signal? a) To set a default value b) To pass value between circuits c) To declare a variable d) To represent local information ans:b

What is the use of a variable? a) To represent local value b) To represent default value c) To set default value d) To declare a subprogram ans:a Use of constants is to _________ a) Represent wires b) Represent local information c) Represent default value d) Pass value between entities ans:c How to declare a constant in VHDL? a) CONSTANT name : type := value; b) CONSTANT name := value; c) CONSTANT name := type := value; d) CONSTANT name := type : value; ans:a Which of the following can’t be declared in an architecture? a) Signal b) Constant c) Variable d) BIT_VECTOR ans:c

Set 1 clock jitter means A. variation in clock signal B. variation in fan out C. variation in power dissipation D. variation in supply voltage ANSWER:A solution on clock skew problem A. reduce connecting wire B. H tree diagram C. M tree diagram D. none of above ANSWER:B one power optimization technique A. using binary encoding in fsm B. reduce power supply C. reduce glitches in digital design D. reduce connecting wire ANSWER:C floorplanning means A. arrange blocks on chip B. connect two block C. calculate power dissipation D. none of above ANSWER:A WHICH of the following statement is correct A. Gate array based ASIC design by hand B. semi custom asic design by hand C. FPGA is programmed ASIC D. Mix signal ASIC content only digital circuit ANSWER:C placement objective in chip design A. Minimize cross talk between signals B. increasing connecting wires C. increases complexity in connecting wires D. none of above

ANSWER:A global routing means A. minimize total interconnect length B. maximize total interconnect length C. maximize critical path delay D. none of above ANSWER:A WHICH statement is incorrect A. signal integrity due to substrate noise B. EMI reduce by differential clocking system C. EMI reduce by spread spectrum clocking D. global routing is not important in chip design ANSWER:D signal integrity means A. poor clock signal routing B. poor power arrangement C. Inductive crosstalk D. All of above ANSWER:D WHICH STATEMENT is correct A. parasitic induced delays B. signal integrity means clock skew C. pads are not used in chip design D. SRC AND DRC not important in chip design ANSWER:A

SET-2

Before the commencement of design, the clocking strategy determine/s __________ a. Number of clock signals necessary for routing throughout the chip b. Number of transistors used per storage requirement c. Power dissipated by chip & the size of chip d. All of the above

ANSWER: All of the above Which method/s of physical clocking is/are a /the recursive structure where the memory elements are grouped together to make the use of nearby or same distribution points? a. H tree b. Balanced tree clock network c. Both a and b d. None of the above ANSWER: H tree Increase in the physical distance of H-tree _________the skew rate. a. Increases b. Stabilizes c. Decreases d. All of the above ANSWER: Increases Which among the following is/are identical in Mealy & Moore machines? a. Combinational output signal b. Clocked Process c. Both a and b d. None of the above ANSWER: Clocked Process In floorplanning, placement and routing are __________ tools. a. Front end b. Back end c. Both a and b d. None of the above ANSWER: Back end In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and the interconnection density? a. Placement b. Global Routing c. Detailed Routing

d. All of the above ANSWER: Placement In Gray coding, when the state machine changes state, ______ bit/s in the state vector changes the value. a. one b. two c. four d. eight ANSWER: one Output values of Moore type FSM are determined by its ________ a) Input values b) Output values c) Clock input d) Current state ANS:D In FSM diagram what does circle represent? a) Change of state b) State c) Output value d) Initial state ANS:B Hold time is defined as the time required for the data to ________ after the triggering edge of clock. a. Increase b. Decrease c. Remain stable d. All of the above ANS:C

SET-3

The time required for an input data to settle _____ the triggering edge of clock is known as

'Setup Time'. a. Before b. During c. After d. All of the above ANS:A

20) Hold time is defined as the time required for the data to ________ after the triggering edge of clock. a. Increase b. Decrease c. Remain stable d. All of the above ANSWER: Remain stable 24) Before the commencement of design, the clocking strategy determine/s __________ a. Number of clock signals necessary for routing throughout the chip b. Number of transistors used per storage requirement c. Power dissipated by chip & the size of chip d. All of the above ANSWER: All of the above 25) Which method/s of physical clocking is/are a /the recursive structure where the memory elements are grouped together to make the use of nearby or same distribution points? a. H tree b. Balanced tree clock network c. Both a and b d. None of the above ANSWER: H tree Which among the following is/are identical in Mealy & Moore machines? a. Combinational output signal b. Clocked Process c. Both a and b

d. None of the above ANSWER: Clocked Process The full form of VLSI is ____________ a) Very Long Single Integration b) Very Least Scale Integration c) Very Large Scale Integration d) Very Long Scale Integration ANS:C The devices which are based on fusible link or antifuse are _________time/s programmable. a. one b. two c. four d. infinite ANSWER: one 60) In floorplanning, placement and routing are __________ tools. a. Front end b. Back end c. Both a and b d. None of the above ANSWER: Back end 61) In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area and the interconnection density? a. Placement b. Global Routing c. Detailed Routing d. All of the above ANSWER: Placement WHICH of the following statement is correct A. Gate array based ASIC design by hand B. semi custom asic design by hand C. FPGA is programmed ASIC

D. Mix signal ASIC content only digital circuit ANSWER:C

SET 1 SET-1 1) In Programmable Array Logic content A. Programmable AND matrix and fix OR gate B. Fix AND gate and programmable OR gate C. AND matrix and OR matrix both programmabe D. none of above ANSWER:A SET-2 2) CPLD means A. Critical Program Logic Device B. Complex Programmable Logic Device C. Cell based Programmable Logic Device D. Complex Programmable Layout Device ANSWER:B SET-3 3) which statement is correct A. LUT content in CPLD B. LUT content in FPGA C. FPGA is not programmable D. no of flip flop is more in CPLD compare FPGA ANSWER:B SET-1 4) How much mux content in 3 input variable LUT A. 8 B. 11 C. 10 D. 7 ANSWER:D SET-2 20) Which statement is incorrect a) SRAM cells are volatile b) VHDL is hardware description language c) CPLD content LUT d) FPGA content sophisticated clock management ANS:C SET-3 6) How much bit content in 4 input variable LUT A. 16 B. 3 C. 15 D. 14

ANSWER:A SET-1 7) How much mux content in 2 input variable LUT A. 8 B. 3 C. 4 D. 7 ANSWER:B SET-2 8) The complex programmable logic device content several PLD blocks and A. A global interconnect matrix B. field programmable switches C. AND/OR array D. a language compiler ANSWER:A SET-3 9) PLA, CPLD and FPGAs are all which type of devices A. SLD B. PLD C. EPROM D. SRAM ANSWER:B SET-1 10) Select wrong statement A. CPLD consumes more power B. FPGA consumes less power C. CPLD content AND matrix D. Very less registers content in FPGA ANSWER:D

SET-2

SET-2 11) CLB means A. Configurable Logic Block B. Complex Logic Block C. Current Logic Block D. Common Logic Block ANSWER:A

SET-3 12) The difference between a PAL & a PLA is ____________

a) PALs and PLAs are the same thing b) The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has a programmable AND plane c) The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has a programmable AND plane d) The PAL has more possible product terms than the PLA ANS:B SET-1 13) If a PAL has been programmed once ____________ a) Its logic capacity is lost b) Its outputs are only active HIGH c) Its outputs are only active LOW d) It cannot be reprogrammed ANS:D SET-2 14) The FPGA refers to ____________ a) First programmable Gate Array b) Field Programmable Gate Array c) First Program Gate Array d) Field Program Gate Array ANS:B

SET-3 15) The inputs in the PLD is given through ____________ a) NAND gates b) OR gates c) NOR gates d) AND gates ANS:D

SET-1 16) The cells in a FPGA may contain registers, look-up tables and memory A) True B) False ANS: A SET-2 17) The full form of VLSI is ____________ a) Very Long Single Integration b) Very Least Scale Integration c) Very Large Scale Integration d) Very Long Scale Integration ANS:C

SET-3 18) In FPGA, vertical and horizontal directions are separated by ____________ a) A line b) A channel c) A strobe d) A flip-flop ANS:B

2 SET-1 19) Which statement is correct a) CPLD consumes more power b) FPGA consumes more power c) More flip flops in CPLD d) FPGA content AND matrix ans:A

2 SET-2 5) How much mux content in 4 input variable LUT A. 16 B. 3 C. 15 D. 14 ANSWER:c

SET-3

2 SET-3 21) 3 input variable LUT content a) 8 bit ram memory b) 3 bit ram memory c) 16 bit ram memory d) 15 bit ram memory ANS:A

2 SET-1 22) Many companies are transitioning to using FPGAs for their processor designs instead of ASICs. a) FPGA always outperform an ASIC b) The development cycle for FPGA is much shorter c) FPGAs are more space-efficient d) FPGAa are both smaller and faster

ANS: B 2 SET-2 23) Most FPGA logic modules utilize a(n)____________approach to create the desired logic functions. a) AND array b) Look-up table c) OR array d) AND and OR array ans:b

2 SET-3 24) Which gates are used on the output side as buffers in order to provide a programmable output polarity in PAL 16 P8 devices? a. AND b. OR c. EX-OR d. NAND ANS:C 2 SET-2 25) _________ is the fundamental architecture block or element of a target PLD. a. System Partitioning b. Pre-layout Simulation c. Logic cell d. Post-layout Simulation ANS:C

The devices which are based on fusible link or antifuse are _________time/s programmable. a. one b. two c. four d. infinite ANSWER: one 57) Which among the following is/are not suitable for in-system programming? a. EPROM b. EEPROM c. Flash d. All of the above

ANSWER: EPROM 58) Simple Programmable Logic Devices (SPLDs) are also regarded as _____________. a. Programmable Array Logic (PAL) b. Generic Array Logic (GAL) c. Programmable Logic Array (PLA) d. All of the above

ANSWER: All of the above which statement is correct A. LUT content in CPLD B. LUT content in FPGA C. FPGA is not programmable D. no of flip flop is more in CPLD compare FPGA ANSWER:B which following company design PROASIC3 FPGA A. Cypress B. Actel C. Philips D. Xilinx ANSWER:B

MOSFET is in linear region A. Vgs is greater than Vds B. Vgs is smaller than Vds C. Vgs=0V D. None of above ANSWER:A MOSFET saturation region A. Vgs is greater than Vds B. Vds is greater than Vgs C. Vgs=0V D. none of above ANSWER:B N channel MOSFET cutt off state A. Vgs=0v B. Vgs=Vds C. Vgs=5V D. Vgs=Vds=5V ANSWER:A Body effect problem means A. N channel MOSFET body 0V B. P channel MOSFET body 5V C. Source to body voltage greater than 0V D. source to body voltage equal to 0V ANSWER:C Mobility of Electron A. 1000 cm2/V-S B. 230 cm2/v-s C. 2 cm2/v-s D. 580 cm2/v-s ANSWER:D CMOS inverter symmetric when A. (W/L)P=(W/L)n B. (W/L)P=2.5(W/L)n C. length of NMOS transistor greater than PMOS D. channel length of PMOS transistor is greater than NMOS transistor ANSWER:B which statement is wrong for MOS

A. PMOS transistor give strong logic 1 B. NMOS transistor give strong logic 0 C. mobility of electron is smaller than hole D. dynamic power dissipation depends on capacitance ANSWER:C In cmos NAND gate pmos transistor in ___________ A. Series B. Parallel C. Not use PMOS transistor D. None of above ANSWER:B Which parameter is not affect on current A. thickness of sio2 B. mobility C. gate input voltage D. Permitivity of silicon ANSWER:D which statement is wrong for mos A. Threshold voltage depends on sio2 thickness B. threshold voltage depends on doping density C. Threshold voltage depends on drain bias D. Threshold voltage depends on depletion ANSWER:c

In lambda design rule, how much width of polysilicon. A. 2 lambda B. 1 lambda C. 5 lambda D. 3 lambda ANSWER:A Which material is n-type material A. Boron B. Phosphurus C. Gallium D. Indium ANSWER:B In lambda design rule, how much width of metal A. 2 lambda B. 3 lambda C. 4 lambda D. 5 lambda ANSWER:C Which among the following is/are taken account for post-layout simulation A. Interconnect delay B. Propagation delay C. logic cells D. All of above ANSWER:D In floorplanning, placement and routing are __________ tools A. Front load B. back end C. both a and b D. None of the above ANSWER:B Delay of a cell depends on which factors A. Output transition and input load B. Input transition and output load C. Input transition and output transition D. Input load and output load ANSWER:B Cross talk can be avoided by

A. Decreasing the spacing between the metal layers B. shielding the net C. using lower metal layers D. Using long nets ANSWER:B Flicker noise is found in MOSFET at A. Gate and oxide inteface B. Source and substrate interface C. Gate oxide and silicon inteface D. Drain and substrate interface ANSWER:C In CMOS fabriction, the photoresist layer is exposed to A. Visible light B. Flu...