460 Transmit Engine Chip Spec PDF

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CECS 460: System On Chip Design Project 2: Transmit Engine Chip Spec

Asa Marsh December 2, 2019

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Date: December 2, 2019

Revision: 1.0

Table of Contents I. Introduction………..……………………………………………………...……………Page 3 II. Documents………..……………………………………………………...……………Page 4 III. Requirements...…..……………………………………………………...……………Page 5 IV. Top Level Design..……………………………………………………...……………Page 6 V. Transmit Engine………………………………………………………………….….Page 10 VI. Baud Decoder……………………………………………………………………….Page 12 VII. TramelBlaze……...…………………………………………………...……………Page 14 VIII. Appendix………..…………………………………………………...……………Page 15

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I.

Date: December 2, 2019

Revision: 1.0

Introduction

The design documented in this report is that of a UART transmit engine that is connected to a 16bit embedded microcontroller in order to send specific data from the Nexys 4 FPGA to the host machine using serial communication. The embedded microcontroller used is the TramelBlaze, which emulates the function of the Xilinx PicoBlaze; the differences between the TramelBlaze and the PicoBlaze will be discussed in Section V.

I.1

Purpose

The purpose of this design is to communicate data serial from the FPGA to the host machine. The message being transmitted reads “CSULB CECS 460-[COUNT]” where [COUNT] is a five-digit number that starts at 00000 and increases by one every time that a complete line is transmitted. While not transmitting a message, the LEDs are walked through one at a time.

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II.

Documents

II.1

External Documents

Revision: 1.0

Nexys 4™ FPGA Board Reference Manual https://reference.digilentinc.com/_media/nexys:nexys4:nexys4_rm.pdf

PicoBlaze User Guide https://www.xilinx.com/support/documentation/ip_documentation/ug129.pdf

II.2

Internal Documents

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III.

Date: December 2, 2019

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Requirements

Requirement ID

Requirement Description

1 2 3

Perform transmit function of UART. Walk 1 bit through LEDs while in TramelBlaze main function. Display message “CSULB CECS 460 –[COUNT]” where count starts at 0 and

4 5 6 7

increases by one for every new line, from 0 – 99,999. Operate at the baud rates listed in the table on Page 12 Operate with either 7 or 8 bit message. Operate with optional polarity bit. Operate with polarity select, choosing between even and odd polarity.

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IV.

Top Level Design

IV.1

Description

Revision: 1.0

This design consists of two major components; the TramelBlaze and the Transmit Engine. The Transmit Engine receives an 8-bit word from the TramelBlaze and sends that words to the host machine, one bit at a time. After the Transmit Engine has finished transmitting the word, it signals to the TramelBlaze, through the TxRdy signal triggering the TramelBlaze interrupt, that it is ready for another word. A flop is used to control the interrupt signal so that it is acknowledged after triggering as well as to ensure there isn’t another interrupt while the current word is being transmitted. A PED, or Positive-Edge-Detect, module is used to send a 1-clock wide signal to the mentioned flop only when TxRdy transitions from low to high.

The design can be controlled to transmit data through different protocols. It is possible to transfer either a 7-bit word or an 8-bit word. It is possible to enable or disable the inclusion of a polarity bit. It is also possible to choose whether the polarity of the data transferred is to be odd or even. Lastly, it is possible to select between twelve different baud rates ranging from 300 to 921,600.

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IV.2

Date: December 2, 2019

Block Diagram

Source: John Tramel, CECS 460 Fall 2019

Revision: 1.0

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IV.4

I/O

IV.4.1

Signal Names

Revision: 1.0

Inputs clk – The clk is the 100MHz clock supplied by the FPGA. rst – Global reset used to initialize the design or restart operation. baud – A four-bit code used to determine comparator value which generates baud rate. eight – Determines if data sent is 7-bits (low) or 8-bits (high). pen – Determines if polarity bit generation is enabled. ohel – Determines type of polarity generated. Odd (high) or even (low). Outputs tx – Single bit of transmit data. leds – Signal used to drive on board LED’s.

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IV.4.2

Date: December 2, 2019

Revision: 1.0

Pin Assignments

Signal Name

Pin Location

clk rst baud[0] baud[1] baud[2] baud[3] eight pen ohel tx

E3 N17 R17 T18 U18 R13 R15 M13 L16 D4

Signal Name

Pin Location

leds[0] leds[1] leds[2] leds[3] leds[4] leds[5] leds[6] leds[7] leds[8] leds[9] leds[10] leds11] leds[0] leds[0] leds[0] leds[0]

H17 K15 J13 N14 R18 V17 U17 U16 V16 T15 U14 T16 V15 V14 V12 V11

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VI

Transmit Engine

VI.1

Description

Revision: 1.0

The Transmit Engine is given data, which comes from the TramelBlaze, and then transmits it serially through the FPGA UART port where it is received by the host machine. The Transmit Engine has a TxRdy signal which interrupts the TramelBlaze, announcing it is ready to send a set of data. This transmit engine can optionally send either 7 or 8-bits of data. There is also the option to include a polarity bit as well as the option to choose if the polarity should be even or odd. After the txrdy signal has gone high, a load signal will determine when the data from the TramelBlaze is loaded into the Transmit Engine shift register. The decoded baud signal is used to generate the correct timing through the two comparator setups. Using this timing, the shift registers shifts data to the right and the LSB is used to drive the tx output.

VI.2

Block Diagram

Source: John Tramel, CECS 460 Fall 2019

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VI.3

Date: December 2, 2019

Revision: 1.0

I/O

Signal Name Input

Description

clk rst k word load

100MHz clock supplied by FPGA. Universal reset used to initialize design. 19-bit value used in comparator to generator baud timing. The data to be transferred. Shift register load control. Loads new data to be transferred into the

eight pen ohel

shift register. Control signal determining if data sent is 7-bits (low) or 8-bits(high). Control signal determining if a polarity bit is sent with the data. Control signal determining if polarity of message should be odd (high) or even (low).

Output txrdy tx

VI.4

Signals the transmit engine is ready to send data. The serial data being output to the host machine.

Verification

The transmit engine drives itself and therefore can be verified through testing operation.

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VII

Baud Decoder

VII.1

Description

Revision: 1.0

The baud decoder is a decoder which take a 4-bit input and outputs a 19-bit signal used to generate the baud timing for the transmit engine. The input to the baud decoder comes from the on-board switches and the input represents a desired baud value for the transmit engine to operate at, a chart of these values is given below. The baud decoder assumes that the design is driven by the FPGA 100MHz clock, therefore, the k values generated are those needed to drive a clock-divider circuit, which is built in to the tx module.

VII.2

baud[3:0]

Rate

k

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011

300 1200 2400 4800 9600 19,200 38,400 57,600 115,200 230,400 460,800 921,600

333,333 83,333 41,667 20,833 10,417 5,208 2,604 1,736 868 434 217 109

Block Diagram

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VII.3

Date: December 2, 2019

Revision: 1.0

I/O

Signal Name Input

Description

baud[3:0]

Code representing the desired baud rate to transmit data at.

Output k[18:0]

Value needed to divide 100MHz clock in order to generate desired baud rate.

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VIII

TramelBlaze

VIII.1

Description

Revision: 1.0

The TramelBlaze is used to control the signaling to the transmit engine in order to properly display the desired lines of text. The txrdy signal is used to trigger the TramelBlaze interrupt, in which one character is selected and output to the transmit engine word input. Since the characters are output in ASCII, the TramelBlaze also has a subroutine in which it converts numbers from binary to the respective ASCII value, before outputting to the transmit engine. In the main function of the TramelBlaze a one is rotated and output to the FPGA LEDs in order to “walk” an LED while not servicing interrupts.

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Appendix Source Code top_level.v

Date: December 2, 2019

Revision: 1.0

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baud_decoder.v

Date: December 2, 2019

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tx.v

Date: December 2, 2019

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ped.v

Date: December 2, 2019

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transmit_engine.ucf

Date: December 2, 2019

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transmit_engine.tba

Date: December 2, 2019

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