6) ans-works 5-isatwo - worksheet PDF

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CMSC 411 Computer Architecture Worksheet 5 MIPS64 ISA Two Draft Answers Dr. Michelle McElvany Hugue Reading And Writing MIPS64 Code Fragments We hope you enjoy analyzing yet another MIPS64 code fragment, because you are going need to use your brand new knowledge to write some MIPS64 code fragments on your own in the 2nd half of the quiz. The code fragments that you are to analyze in problem 1 and to write in problem 2 are to be run on a byte addressable Big Endian MIPS64 ISA using the assumptions and instructions contained on the separate Week 5 Resource sheet. You should expect a similar sheet for use with Test 1.

Part 1: Gnarly Options The code fragment that follows written for a byte addressable Big Endian MIPS64 that satisfies the assumption that instruction (1) is located at memory address 720010 Address 720010

Addressing Mode (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11)

crack:

ice:

DADDI DADDI LD DADDI DADD XOR SUBD SD BEQZ J SD

MIPS Ins Type

R1, R0, #-4 R6,R1, #5 R2, 255(R6) R5, R0, #-1 R6, R6, R1 R2, R2, R5 R2, R2, R5 -1021(R6), R2 R6, ice crack 64(R2), R1

1.1 For each instruction in the code fragment above, write the type of register addressing mode and the MIPS instruction type in the appropriate columns. Answers: Addressing Modes: Register 5, 6, 7; Immediate 1, 2, 4, 10(?); Displacement 3, 8, 11. MIPS Instruction Type: R Type 5,6,7 I Type 1, 2, 3, 4, 8, 9, 11; J Type 10. A most 3 points of 10 if you gave any other description of these instructions, such as ALU, Branch, Jump, Memory. 1.2 How much memory do these eleven (11) lines of MIPS code occupy? Answer: 44 bytes: 4 bytes per instruction times 11 instructions. 11 words is also acceptable. 1.3 In instruction (8), what is the address of the byte(s) containing the immediate operand -1021? Be specific in indicating the address of the MSB and the LSB of the constant operand for full credit. Answer: Code fragment starts at address 720010 . Each instruction is 4-bytes long, and memory is byte-addressable. So, instruction (7) takes up the 4-bytes beginning with address 7228. Since MIPS is Big Endian, the opcode and 2-register numbers are at byte addresses 7228 and 7229. The immediate operand, corresponding to -1021, is at addresses 7230 and 7231. The MSB (the byte containing the sign bit) of the immediate operand is in the byte at address 7230, while the LSB is in the byte at address 7231.

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1.4 How is the label ice represented when instruction (9) is encoded? Be as specific as possible. (Hint: what types of addressing modes do we have?) Answer: Since conditional branches cannot use Register or Displacement addressing mode, or R-type or J-type (why not?), they must be Immediate. That means that the 16-bit immediate operand in the two low-order bytes of instruction (8) correspond to the label, and will be added to the program counter, or perhaps shifted left by 2 and then added to the program counter, since the book isn’t consistent on this. So, it’s sufficient for you to say that when the the immediate operand portion of the associated Immediate instruction and the PC value are combined, the result is the address of the instruction labeled ice. This handles the fact that t the address of that instruction is too small to fit in a 16bit(2byte) immediate field of a 32bit (4byte) MIPS instruction. In fact, the location of the target instruction must be computed since the value of the PC is not known until runtime. 1.5 What is in R2 after instruction (7) is completed, assuming that the content of R5 is subtracted from R2. Be as specific as possible–a description is just fine. Answer: The original contents of register R2 are replaced by the bit-wise complement of R2 minus -1 which adds one to R2 and is , also known as the 2’s complement of R2. 1.6 What is the bit pattern in the 64 bit register R1 after instruction (1) has been executed? For brevity and consistency, please express your answer in hexadecimal assuming that the least significant bit of its binary equivalent is the rightmost bit, and the most significant bit of its binary equivalent is the leftmost bit. Answer: The command uses immediate addressing mode. So, the 16-bit value in the immediate field of the that instruction will be sign extended . that means that the resulting 64 bit (8 byte) wide register will contain 0x FFFF FFFF FFFF FFFC. 1.7 Ignoring any syntax errors which you would not be able to identify yet anyway, , are any additional assumptions necessary to ensure that this code exhibits the desired run-time behavior? If you think not, circle the word: None. Otherwise, explain for full credit. Answer: The only error of which I am aware has to do with byte alignment. All MIPS memory accesses of k-byte objects must have addresses that are 0 mod k. So, the value in register R1 in instructions (6) and (7) must be 0 mod 8 since the immediate operand associated with the displacement -32768 is known to be 0 mod 8. Since we don’t know the value of R2, we could only infer k-byte alignment from assuming an appropriate initial value for R2.

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Problem 2: Make Mine MIPS Write MIPS64 code fragments that satisfy the following post conditions or “after execution” requirements. Or, if no such fragment can be constructed, explain why. Assume that we are using a Big Endian version of MIPS64. Be sure to use the assumptions on page two of the worksheet and the 2.1 Write a MIPS64 code fragment with the post condition that register R1 contains the two’s complement representation of −110 Answer: After the code fragment has completed, which is what we mean by “. . . the post condition. . . ”, register R1 should contain the 64-bit 2’s complement representation of −210 . This is exactly what signextending a 16-bit 2’s complement representation of −210 accomplishes. DADDI

R1, R0, #-1

Note that to obtain the 2’s complement representation of −110 directly, we would start with a 64 bit 1 (that’s 63 0’s with a 1 on the right). Next, we complement those 64 bits, with the 0’s becoming 1’s and vice versa. This can be done by computing the XOR of that bit pattern with a string consisting of 64 1’s, and then adding a 1 at the least significant bit position. This would produce 64 1’s, which is the two’s complement representation of −110 . Remember: 2’s complement is a representation of integers as well as a method to decode a bit string with a sign bit of 1, or to produce the 2’s complement version of a negative integer. 2.2 Write a MIPS64 code fragment that will load R2 with the 8 byte word at a memory address that is 255 bytes after the contents of register R6. Answer: LD R2, 255(R6) 2.3 Write a MIPS64 code fragment that transfers control to an instruction labelled ice when register R6 contains a zero. Answer:

BEQZ R6, ice

2.4 Write a MIPS64 code fragment with the post condition that the memory location in register R23 contains the contents of register F23. Answer: This answer includes a sneaky little trick of using displacement addressing mode to “simulate” register indirect. S.D 0(R23), F23 or S.D F23, 0(R23) receives full credit. 2.5 Write a MIPS64 code fragment with the post condition that register R7 contains the bit pattern below: 0x0000 0000 0000 FFFE Answer: It’s time to learn something new. One correct answer DADDI R6, R0, 0x7FFF SLL R7, R6, #1 Shift left by 1 bit position. Here is an incorrect answer Specify the bit pattern for -2 in two’s complement, DADDUI R2, R0, #0xFFFE which is equivalent to specifying -2 as the immediate operand in base 10.

DADDUI R2, R0, #-2

Why are they wrong? The problem is with the unfortunate name of “unsigned” for the two immediate add functions. Unsigned does not disturb sign extension–the sign bit of 1 in each of them is copied to produce 64bits. The effect of the unsigned suffix is that no exception for overflow occurs at any time. 3

Instead, the sum wraps around the max value of all ones to all zeros and increases from there. Think of it as being like modular arithmetic. What is correct? Well, to get a bit pattern where the top 48 bits are 0, you need to use a 16 bit constant with 0 as a sign bit. The bit pattern of the largest positive immediate operand would be the bit pattern corresponding to 0x7F F F which is equivalent to 215 − 1 or positive 32767. That doesn’t mean it is always the correct bit pattern to start with–merely the largest one. 2.6 Write a MIPS64 code fragment that transfers a 4 byte word from memory address 0xFF00 00FF into register R16 Answer: There is no MIPS64 code fragment which will load register R16 with an 8-byte, 4-byte, or 2-byte multi-byte word from that location without crashing the machine. Why? Because MIPS64 requires byte aligned access, and the address given will be valid for single byte objects. This is one of the more annoying code fragments that I request. First and foremost, that memory address is a 32-bit unsigned bnary number which cannot be created by 0-extending or sign-extending any 16 bit constant. So, you try to figure out how to produce that desired bit pattern using ALU operands and 16-bit operands. Then, you get annoyed. Really annoyed. After all, how many problems require you to create bit patterns from big numbers? This time the hard part was recognizing that the byte alignment was the important part of the question. 2.7 Write a MIPS64 code fragment that swaps the contents of registers R4 amd F4. A full credit answer will use only int ALU, load, and store operations. At most half credit for using one of the Move operations. Answer: This is not as tricky as it may seem, given that integer registers (R0-R31) and floating point registers (F0–F31) cannot appear together in the same ALU instruction. The trick is to use memory for temporary storage. Assuming that nothing interesting is in memory at addresses 16 or 64, One acceptable solution SD 16(R0), R4 S.D 64(R0), F4 LD R4, 64(R0) L.D F4, 16(R0) In fact, the above assumption can be removed by saving the contents of addresses 16 and 64 on the stack, because if you put them in registers, you have to make assumptions about the contents of the temporary registers. 2.8 Write a MIPS64 code fragment that initializes register R23 to 218 . Answer: The challenge here is to get register R23 to contain the bit pattern corresponding to 0x0000 0000 0002 0000, which will not fit into 16 bits since it has 16 0’s as its least significant bits, which is the size of the Immediate operand. What does work DADDI R20, R0, #0x4000 SLL R23, R20, #4 since sign extend on 0x4000 zero fills, shifting the 64 bit guy left 4 bits puts gets you the 0x0000 0000 0002 0000 you need. (a 1 in the proper bit position). Alternatively, put a 1 in the lsb (that’s least significant bit) position of R23, which corresponds to the coefficient of 20 . Then, shift R23 left 18 times which makes the coefficient of 218 1, with all the other bits zero. DADDI R23, R0, #1 SLL R23, R23, #18

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And, check to make sure, since I’m somewhat allergic to numbers, but i think that LUI R23, 2 should work. (Correct me if this is wrong, please) What doesn’t work, and why. • The number 6553510 ≡ 216 − 1 it is 16 one’s in unsigned binary, but will need 17 bits in 2’s complement (a sign bit and the 16 bits that are part of the magnitude), and it will be interpreted as the bit pattern 0xFFFF in 2’s complement, which will sign extend and be -1 all day. So it’s too big for 16 bits in an I-type mips instruction. • The number

−3276810 ≡ −215

is the most negative number in 16bit 2’s complement, with bit pattern equivalent to 0x8000. It sign fills with 1 to maintain the base 10 value of ‘-32768 with the bit pattern equivalent to 0xFFFF FFFF FFFF 8000 • The number 3276710 ≡ 215 − 1 is a 0 in the most significant byte folllowed by 15 ones. It can be used to make some constants with lots of zeros beause it’s zero filled. 2.9 Write a MIPS64 code fragment that stores the contents of register F16 at an address with a bit pattern computed by adding -32768 to the contents of register R1. Answer: The instruction is derived by recognizing that the text above is equivalent to the following instruction: S.D F16, -32768(R1) But, will the constant or displacement fit into the 16 bits of a MIPS I-type instruction? Yes, as discussed in the detailed note below, the 16 bit immediate operand consisiting of a 1 followed by 15 zeroes has the desired properties because the extension by 1’s doesn’t change the sign or magnitude of the value adeded to the contents of R1. This is yet another exploration of your ability to read English and to generate a correct bit pattern. The trick it to exploit what you know your boundary bit patterns for 16 bit Immediates. Unsigned binary from 16 bits is in the range of (unsigned) whole numbers from 0 to 6553510 ≡ (216 − 1), corresponding to bit patterns 16 zeroes and 16 ones, respectively. Two’s complement integers with 16 bits range from −3276810 (1 followed by 15 zeroes) to +3276710 (0 followed by 15 ones). 1xshel 2.10 Write a MIPS64 code fragment that will put the sum of the first 6 odd integers greater than 0 in register R20. Answer: All you have to do is make sure that R22 contains 36, the sum of the first 6 odd positive integers. DADDI R20, R0, #36 In mips, we often initialize integer registers using ALU instructions, the fact that R0 contains zero, and immediate operands

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