74HC HCT00 3 eee2000 1 Digital electronics and design PDF

Title	74HC HCT00 3 eee2000 1 Digital electronics and design
Author	Jason Jackobs
Course	Digital Electronics Design
Institution	Swinburne University of Technology
Pages	17
File Size	566.9 KB
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Summary

These are given to be able to use in modules...

Description

INTEGRATED CIRCUITS

DATA SH EET

74HC00; 74HCT00 Quad 2-input NAND gate Product specification Supersedes data of 1997 Aug 26

2003 Jun 30

Philips Semiconductors

Product specification

Quad 2-input NAND gate

74HC00; 74HCT00 DESCRIPTION

FEATURES

The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

Complies with JEDEC standard no. 8-1A ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V

The 74HC00/74HCT00 provide the 2-input NAND function.

Specified from 40 to +85 C and 40 to +125 C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH CI

propagation delay nA, nB to nY input capacitance

CL = 15 pF; VCC = 5 V

CPD

power dissipation capacitance per gate notes 1 and 2

TYPICAL 74HC00

74HCT00

7 3.5

10 3.5

ns pF

22

22

pF

Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD

VCC2

fi

VCC2

N + (CL

fo) where:

fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL

VCC2

fo) = sum of the outputs.

2. For 74HC00 the condition is VI = GND to VCC. For 74HCT00 the condition is VI = GND to VCC

1.5 V.

FUNCTION TABLE See note 1. INPUT nA

OUTPUT nB

L

L

H

H

H

H

L

H

H

H

L

1. H = HIGH voltage level; L = LOW voltage level.

2003 Jun 30

nY

L

Note

2

UNIT

Philips Semiconductors

Product specification

Quad 2-input NAND gate

74HC00; 74HCT00

ORDERING INFORMATION PACKAGE TYPE NUMBER

TEMPERATURE RANGE

PINS

PACKAGE

MATERIAL

CODE

74HC00N

40 to +125 C

14

DIP14

plastic

SOT27-1

74HCT00N 74HC00D

40 to +125 C 40 to +125 C

14 14

DIP14 SO14

plastic plastic

SOT27-1 SOT108-1

74HCT00D

40 to +125 C

14

SO14

plastic

SOT108-1

74HC00DB

40 to +125 C

14

SSOP14

plastic

SOT337-1

74HCT00DB 74HC00PW

40 to +125 C 40 to +125 C

14 14

SSOP14 TSSOP14

plastic plastic

SOT337-1 SOT402-1

74HCT00PW

40 to +125 C

14

TSSOP14

plastic

SOT402-1

74HC00BQ

40 to +125 C

14

DHVQFN14

plastic

SOT762-1

74HCT00BQ

40 to +125 C

14

DHVQFN14

plastic

SOT762-1

PINNING PIN

SYMBOL

DESCRIPTION

1

1A

data input

2 3

1B 1Y

data input data output

4

2A

5

handbook, halfpage

1A

1

14 VCC

data input

1B

2

13 4B

2B

data input

1Y

3

12 4A

6 7

2Y GND

data output ground (0 V)

2A

4

2B

5

10 3B

8

3Y

data output

2Y

6

9 3A

9

3A

data input

GND

7

8 3Y

10 11

3B 4Y

data input data output

12

4A

data input

13

4B

data input

14

VCC

supply voltage

2003 Jun 30

00

11 4Y

MNA210

Fig.1

3

Pin configuration DIP14, SO14 and (T)SSOP14.

Philips Semiconductors

Product specification

Quad 2-input NAND gate

handbook, halfpage

1A

VCC

1

14

74HC00; 74HCT00

1B

2

13

4B

1Y

3

12

4A

2A

4

11

4Y

2B

5

10

3B

2Y

6

9

3A

GND(1)

handbook, halfpage

A Y B

Top view

7

8

GND

3Y

MNA211

MNA950

(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.

Fig.2 Pin configuration DHVQFN14.

Fig.3 Logic diagram (one gate).

handbook, halfpage handbook, halfpage

1

&

3

&

6

&

8

&

11

2 1 2

1A 1B

4

2A

5

2B

9 10

3A 3B

1Y

3

2Y

6

3Y

8

4 5

9 10

12 13

4A 4B

4Y

11 12 13

MNA212

MNA246

Fig.5 IEC logic symbol.

Fig.4 Function diagram.

2003 Jun 30

4

Philips Semiconductors

Product specification

Quad 2-input NAND gate

74HC00; 74HCT00

RECOMMENDED OPERATING CONDITIONS SYMBOL

PARAMETER

74HC00

CONDITIONS

TYP.

MAX.

MIN.

TYP.

MAX.

5.0

6.0 VCC

4.5 0

5.0

5.5 VCC

V V

VCC

0

VCC

V

+25

+125

+25

+125

supply voltage input voltage

2.0 0

VO

output voltage

0

operating ambient temperature

tr, tf

input rise and fall times

40

see DC and AC characteristics per device VCC = 2.0 V

UNIT

MIN.

VCC VI Tamb

74HCT00

40

C

1000

VCC = 4.5 V VCC = 6.0 V

6.0

ns

500 400

6.0

500

ns ns

LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL

PARAMETER

CONDITIONS

MIN.

IIK

input diode current

VI < 0.5 V or VI > VCC + 0.5 V

20

mA

IOK

output diode current

IO

VO < 0.5 V or VO > VCC + 0.5 V 0.5 V < VO < V CC + 0.5 V

20 25

mA mA

ICC, IGND Tstg

storage temperature

Ptot

power dissipation

65 Tamb = 40 to +125 C; note 1

Note 1. For DIP14 packages: above 70 C derate linearly with 12 mW/K. For SO14 packages: above 70 C derate linearly with 8 mW/K. For SSOP14 and TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K.

2003 Jun 30

5

+7.0

UNIT

supply voltage

output source or sink current VCC or GND current

0.5

MAX.

VCC

V

50

mA

+150

C

500

mW

Philips Semiconductors

Product specification

Quad 2-input NAND gate

74HC00; 74HCT00

DC CHARACTERISTICS Type 74HC00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL

PARAMETER

TEST CONDITIONS OTHER

MIN.

TYP.

MAX.

UNIT

VCC (V)

Tamb = 40 to +85 C; note 1 VIH

VIL

VOH

VOL

ILI IOZ ICC

2003 Jun 30

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

VI = VIH or VIL IO = 20 A

2.0

1.5

1.2

V

4.5 6.0

3.15 4.2

2.4 3.2

V V

2.0

0.8

0.5

V

4.5

2.1

1.35

V

6.0

2.8

1.8

V

2.0

1.9

2.0

V

IO = 20 A

4.5

4.4

4.5

V

IO = 20 A IO = 4.0 mA

6.0 4.5

5.9 3.84

6.0 4.32

V V

IO = 5.2 mA

6.0

5.34

5.81

V

VI = VIH or VIL IO = 20 A IO = 20 A

2.0 4.5

0 0

0.1 0.1

V V

IO = 20 A

6.0

0

0.1

V

IO = 4.0 mA

4.5

0.15

0.33

V

IO = 5.2 mA VI = VCC or GND

6.0 6.0

0.16

0.33 1.0

V A

.5.0

A

input leakage current 6.0 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current VI = VCC or GND; IO = 0 6.0

6

20

A

Philips Semiconductors

Product specification

Quad 2-input NAND gate

SYMBOL

PARAMETER

74HC00; 74HCT00

TEST CONDITIONS OTHER

VCC (V)

MIN.

TYP.

MAX.

UNIT

Tamb = 40 to +125 C VIH

VIL

VOH

VOL

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

VI = VIH or VIL IO = 20 A

2.0

1.5

V

4.5 6.0

3.15 4.2

V V

2.0

0.5

V

4.5

1.35

V

6.0

1.8

V

2.0

1.9

V

IO = 20 A IO = 20 A IO = 4.0 mA

4.5

4.4

V

6.0 4.5

5.9 3.7

V V

IO = 5.2 mA

6.0

5.2

V

VI = VIH or VIL IO = 20 A IO = 20 A

2.0 4.5

0.1 0.1

V V

IO = 20 A

6.0

0.1

V

IO = 4.0 mA

4.5

0.4

V

IO = 5.2 mA VI = VCC or GND

6.0 6.0

0.4 1.0

V A

ILI

input leakage current

IOZ

6.0 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current VI = VCC or GND; IO = 0 6.0

ICC Note

1. All typical values are measured at Tamb = 25 C.

2003 Jun 30

7

10.0 40

A A

Philips Semiconductors

Product specification

Quad 2-input NAND gate

74HC00; 74HCT00

Type 74HCT00 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL

TEST CONDITIONS

PARAMETER

OTHER

VCC (V)

MIN.

TYP.

MAX.

UNIT

Tamb = 40 to +85 C; note 1 VIH

HIGH-level input voltage

4.5 to 5.5

VIL

LOW-level input voltage

4.5 to 5.5

VOH

HIGH-level output voltage

VOL

LOW-level output voltage

VI = VIH or VIL IO = 20 A IO = 4.0 mA

4.5 4.5

VI = VIH or VIL IO = 20 A IO = 4.0 mA

4.5 4.5 5.5

ILI

input leakage current

VI = VCC or GND

IOZ

3-state output OFF current

ICC

quiescent supply current

5.5 VI = VIH or VIL; VO = VCC or GND; IO = 0 VI = VCC or GND; 5.5 IO = 0 VI = VCC 2.1 V; 4.5 to 5.5 IO = 0

ICC

additional supply current per input

2.0

1.6 1.2

4.4 3.84

V 0.8

4.5 4.32 0 0.15

150

V V V

0.1 0.33

V V

1.0

A

5.0

A

20

A

675

A

Tamb = 40 to +125 C VIH

HIGH-level input voltage

4.5 to 5.5

VIL

LOW-level input voltage

4.5 to 5.5

VOH

HIGH-level output voltage

VOL

LOW-level output voltage

ILI

input leakage current

IOZ

3-state output OFF current

ICC

quiescent supply current

ICC

additional supply current per input

V 0.8

V

VI = VIH or VIL IO = 20 A IO = 4.0 mA

4.5 4.5

VI = VIH or VIL IO = 20 A

4.5

0.1

V

IO = 4.0 mA VI = VCC or GND

4.5 5.5

0.4 1.0

V A

10

A

5.5 VI = VIH or VIL; VO = VCC or GND; IO = 0 VI = VCC or GND; 5.5 IO = 0 VI = VCC 2.1 V; 4.5 to 5.5 IO = 0

Note 1. All typical values are measured at Tamb = 25 C.

2003 Jun 30

2.0

8

4.4 3.7

V V

40

A

735

A

Philips Semiconductors

Product specification

Quad 2-input NAND gate

74HC00; 74HCT00

AC CHARACTERISTICS Type 74HC00 GND = 0 V; tr = tf = 6 ns; CL = 50 pF. SYMBOL

TEST CONDITIONS

PARAMETER

WAVEFORMS

VCC (V)

MIN.

TYP.

MAX.

UNIT

Tamb = 40 to +85 C; note 1 tPHL/tPLH

t THL/tTLH

propagation delay nA, nB to nY

see Fig.6

2.0

25

115

ns

see Fig.6 see Fig.6

4.5 6.0

9 7

23 20

ns ns

2.0

19

95

ns

output transition time

4.5

7

19

ns

6.0

6

16

ns

Tamb = 40 to +125 C tPHL/tPLH

tTHL/tTLH

propagation delay nA, nB to nY

see Fig.6

2.0

135

ns

see Fig.6

4.5

27

ns

see Fig.6

6.0 2.0

23 110

ns ns

4.5

22

ns

6.0

19

ns

TYP

MAX.

UNIT

12

24

ns

29

ns

output transition time

Note 1. All typical values are measured at Tamb = 25 C. Type 74HCT00 GND = 0 V; tr = tf = 6 ns; CL = 50 pF SYMBOL

TEST CONDITIONS

PARAMETER

WAVEFORMS

VCC (V)

MIN.

Tamb = 40 to +85 C; note 1 tPHL/tPLH

propagation delay nA, nB to nY

tTHL/tTLH

output transition time

see Fig.6

4.5 4.5

Tamb = 40 to +125 C tPHL/tPLH

propagation delay nA, nB to nY

tTHL/tTLH

output transition time

see Fig.6

Note 1. All typical values are measured at Tamb = 25 C.

2003 Jun 30

9

4.5

29

ns

4.5

22

ns

Philips Semiconductors

Product specification

Quad 2-input NAND gate

74HC00; 74HCT00

AC WAVEFORMS

VI

handbook, halfpage

nA, nB input

VM

GND t PHL

t PLH

VOH VM

nY output VOL

t THL

t TLH MNA218

74HC00: VM = 50%; VI = GND to VCC. 74HCT00: VM = 1.3 V; VI = GND to 3 V.

Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays.

2003 Jun 30

10

Philips Semiconductors

Product specification

Quad 2-input NAND gate

74HC00; 74HCT00

PACKAGE OUTLINES DIP14: plastic dual in-line package; 14 leads (300 mil)

SOT27-1

ME

seating plane

D

A2

A

A1

L

c e

Z

w M

b1

(e 1 ) b 14

MH

8

pin 1 index E

1

7

0

5

10 mm

scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT

A max.

A1 min.

A2 max.

b

b1

c

D (1)

mm

4.2

0.51

3.2

1.73 1.13

0.53 0.38

0.36 0.23

19.50 18.55

inches

0.17

0.02

0.13

0.068 0.044

0.021 0.015

0.014 0.009

0.77 0.73

(1)

e

e1

L

ME

MH

w

Z max.

6.48 6.20

2.54

7.62

3.60 3.05

8.25 7.80

10.0 8.3

0.254

2.2

0.26 0.24

0.1

0.3

0.14 0.12

0.32 0.31

0.39 0.33

0.01

0.087

E

(1)

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES

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