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VELTECH MULTI TECH DR.RANGARAJAN DR.SAKUNTHALA ENGINEERING COLLEGE DEPARTMENT OF CSE CS8491 COMPUTER ARCHITECTURE EXERCISE PROBLEMS

1. numerical example of booth’s algorithm is shown below for n = 4. It shows the step by step multiplication of -5 and -7. MD = -5 = 1011, MD = 1011, MD'+1 = 0101 MR = -7 = 1001 The explanation of first step is as follows: Qn+1 AC = 0000, MR = 1001, Qn+1 = 0,

SC = 4

Qn Qn+1 = 10 So, we do AC + (MD)'+1, which gives AC = 0101 On right shifting AC and MR, we get AC = 0010, MR = 1100 and Qn+1 = 1 OPERATION

AC

MR

QN+1

SC

0000

1001

0

4

AC + MD’ + 1

0101

1001

0

ASHR

0010

1100

1

AC + MR

1101

1100

1

ASHR

1110

1110

0

2

ASHR

1111

0111

0

1

AC + MD’ + 1

0010

0011

1

0

3

Product is calculated as follows: Product = AC MR Product = 0010 0011 =

35

2. Multiply 14 times -5 using 5-bit numbers (10-bit result). 14 in binary: 01110 -14 in binary: 10010 (so we can add when we need to subtract the multiplicand) -5 in binary: 11011 Expected result: -70 in Multiplicand Action

Multiplier

binary: 11101 11010 Step 01110 01110

0 1

Initialization 10: Subtract Multiplicand

Shift Right Arithmetic 2 Shift Right Arithmetic 3

01110

11001 01101 1 11: No-op 11100 10110 1 01: Add Multiplicand

Shift Right Arithmetic 4

01110

00101 01011 0 10: Subtract Multiplicand

Shift Right Arithmetic 5 Shift Right Arithmetic

01110

11011 10101 1 11: No-op 11101 11010 1

01110

3.Perform Division Restoring Algorithm Dividend = 11 Divisor

= 3 N

4

3

2

M

A

Q

OPERATION

00011

00000

1011

initialize

00011

00001

011_

shift left AQ

00011

11110

011_

A=A-M

00011

00001

0110

Q[0]=0 And restore A

00011

00010

110_

shift left AQ

00011

11111

110_

A=A-M

00011

00010

1100

Q[0]=0

00011

00101

100_

shift left AQ

00011

00010

100_

A=A-M

upper 5-bits 0, lower 5-bits multiplier, 1 “Booth bit” initially 0 00000 11011 0 00000+10010=10010 10010 11011 0 11001 01101 1 11100+01110=01010 (Carry ignored because adding a positive and negative number cannot overflow.) 01010 10110 1 00101+10010=10111 10111 01011 0 11011 10101 1

N

1

M

A

Q

OPERATION

00011

00010

1001

Q[0]=1

00011

00101

001_

shift left AQ

00011

00010

001_

A=A-M

00011

00010

0011

Q[0]=1

4. In this problem, Dividend (A) = 101110, ie 46, and Divisor (B) = 010111, ie 23.

Initialization : Set Register A = Dividend = 000000 Set Register Q = Dividend = 101110 ( So AQ = 000000 101110 , Q0 = LSB of Q = 0 ) Set M = Divisor = 010111, M' = 2's complement of M = 101001 Set Count = 6, since 6 digits operation is being done here.

After this we start the algorithm, which I have shown in a table below : In table, SHL(AQ) denotes shift left AQ by one position leaving Q0 blank. Similarly, a square symbol in Q0 position denote, it is to be calculated later

5. Example addition in binary Perform 0.5

+ (-0.4375) 0.5 = 0.1 × 20 = 1.000 × 2-1

(normalised)

-0.4375 = -0.0111 × 20 = -1.110 × 2-2

(normalised)

1. Rewrite the smaller number such that its exponent matches with the exponent of the larger number. -1.110 × 2-2 = -0.1110 × 2-1

2. Add the mantissas: 1.000 × 2-1 + -0.1110 × 2-1 = 0.001 × 2-1

3. Normalise the sum, checking for overflow/underflow: 0.001 × 2-1 = 1.000 × 2-4 -126 (-3 + 127)

2. Multiply the mantissas 1.000 × 1.110 ----------0000 1000 1000 + 1000 ----------1110000

===> 1.110000

The product is 1.110000 × 2-3 Need to keep it to 4 bits 1.110 × 2-3

3. Normalise (already normalised) At this step check for overflow/underflow by making sure that -126...