CEC222 Pre-Lab 11 PDF

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PreLab for report 11...

Description

Prescott, Arizona Campus Department of Electrical and Computer Engineering CEC 222 Digital Circuit Design Laboratory Student Name: Ismael Vizcarra

Pre-Lab # 11

Date: Monday, March 30, 2020

1) In the following circuit, the 74LS590 counter runs freely from 0 to 25510 and repeats. For each 256 count cycle, for how many clock periods (i.e. counts) are signals A, B and C = ‘1’?

A =’1’ during ___16___ clock periods. B =’1’ during ___2____ clock periods. C =’1’ during ___18____ clock periods. 2) Do any of the periods when A=’1’ and B=’1’ occur simultaneously? Why or why not? This will never occur because A becomes a 1 for QD’ and B for QD. They will never simultaneously equal 1. 3) What Altera (Intel) FPGA part is used on the DE-10-Lite development board? The board utilizes the MAX 10 FPGA. 4) Report these numbers for the FPGA (hint: use Mouser.com or Digikey.com)… Average price for 1 piece

About $93

Number of Logic Array Blocks (aka CLB)

1 (LAB-wide control block)

Number of Logic Elements

16

Total RAM Bits

32

Number of I/O ports

2

CEC 222 Digital Lab Maximum Operating Frequency

Spring 2020 450 MHz

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