Chap05 - Lecture notes Chapter 5 PDF
| Title | Chap05 - Lecture notes Chapter 5 |
|---|---|
| Course | Introduction To Computer Science |
| Institution | Kent State University |
| Pages | 42 |
| File Size | 984.9 KB |
| File Type | |
| Total Downloads | 100 |
| Total Views | 158 |
Summary
Computer Systems Organization. Fall 2007. ...
Description
Invitation to Computer Science, C++ Version, Third Edition
! In this chapter, you will learn about:
The components of a computer system
Putting all the pieces together – the Von Neumann architecture
The future: non-Von Neumann architectures
Computer organization examines the computer as a collection of interacting “functional units”
Functional units may be built out of the circuits already studied
Higher level of abstraction assists in understanding by reducing complexity
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Figure 5.1 The Concept of Abstraction
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Von Neumann architecture has four functional units:
Memory
Input/Output
Arithmetic/Logic unit
Control unit
Sequential execution of instructions
Stored program concept
Figure 5.2 Components of the Von Neumann Architecture
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Information stored and fetched from memory subsystem
Random Access Memory maps addresses to memory locations
Cache memory keeps values currently in use in faster memory to speed access times
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RAM (Random Access Memory)
Memory made of addressable “cells”
Current standard cell size is 8 bits
All memory cells accessed in equal time
Memory address
Unsigned binary number N long
Address space is then 2N cells
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Figure 5.3 Structure of Random Access Memory
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Parts of the memory subsystem
Fetch/store controller
Fetch: retrieve a value from memory
Store: store a value into memory
Memory address register (MAR)
Memory data register (MDR)
Memory cells, with decoder(s) to select individual cells
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Fetch operation
The address of the desired memory cell is moved into the MAR Fetch/store controller signals a “fetch,” accessing the memory cell The value at the MAR’s location flows into the MDR
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Store operation
The address of the cell where the value should go is placed in the MAR The new value is placed in the MDR Fetch/store controller signals a “store,” copying the MDR’s value into the desired cell
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Memory register
Very fast memory location
Given a name, not an address
Serves some special purpose
Modern computers have dozens or hundreds of registers
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Figure 5.7 Overall RAM Organization
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Memory access is much slower than processing time
Faster memory is too expensive to use for all memory cells
Locality principle
Once a value is used, it is likely to be used again
Small size, fast memory just for values currently in use speeds computing time
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Communication with outside world and external data storage
Human interfaces: monitor, keyboard, mouse Archival storage: not dependent on constant power
External devices vary tremendously from each other
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Volatile storage
Information disappears when the power is turned off Example: RAM
Nonvolatile storage
Information does not disappear when the power is turned off Example: mass storage devices such as disks and tapes
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Mass storage devices
Direct access storage device
Hard drive, CD-ROM, DVD, etc.
Uses its own addressing scheme to access data
Sequential access storage device
Tape drive, etc.
Stores data sequentially
Used for backup storage these days
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Direct access storage devices
Data stored on a spinning disk
Disk divided into concentric rings (sectors)
Read/write head moves from one ring to another while disk spins Access time depends on:
Time to move head to correct sector
Time for sector to spin to data location
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Figure 5.8 Overall Organization of a Typical Disk
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I/O controller
Intermediary between central processor and I/O devices Processor sends request and data, then goes on with its work I/O controller interrupts processor when request is complete
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Figure 5.9 Organization of an I/O Controller
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Actual computations are performed
Primitive operation circuits
Arithmetic (ADD, etc.)
Comparison (CE, etc.)
Logic (AND, etc.)
Data inputs and results stored in registers
Multiplexor selects desired output
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ALU process
Values for operations copied into ALU’s input register locations All circuits compute results for those inputs Multiplexor selects the one desired result from all values Result value copied to desired result register
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Figure 5.12 Using a Multiplexor Circuit to Select the Proper ALU Result
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Manages stored program execution
Task
Fetch from memory the next instruction to be executed Decode it: determine what is to be done Execute it: issue appropriate command to ALU, memory, and I/O controllers
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Can be decoded and executed by control unit
Parts of instructions
Operation code (op code)
Unique unsigned-integer code assigned to each machine language operation
Address field(s)
Memory addresses of the values on which operation will work
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Figure 5.14 Typical Machine Language Instruction Format
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Operations of machine language
Data transfer
Move values to and from memory and registers
Arithmetic/logic
Perform ALU operations that produce numeric values
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Operations of machine language (continued)
Compares
Set bits of compare register to hold result
Branches
Jump to a new memory address to continue processing
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Parts of control unit
Links to other subsystems
Instruction decoder circuit
Two special registers:
Program Counter (PC)
Stores the memory address of the next instruction to be executed
Instruction Register (IR)
Stores the code for the current instruction
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Figure 5.16 Organization of the Control Unit Registers and Circuits
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Subsystems connected by a bus
Bus: wires that permit data transfer among them
At this level, ignore the details of circuits that perform these tasks: Abstraction!
Computer repeats fetch-decode-execute cycle indefinitely
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Figure 5.18 The Organization of a Von Neumann Computer
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Physical limitations on speed of Von Neumann computers
Non-Von Neumann architectures explored to bypass these limitations
Parallel computing architectures can provide improvements: multiple operations occur at the same time
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SIMD architecture
Single instruction/Multiple data
Multiple processors running in parallel
All processors execute same operation at one time
Each processor operates on its own data
Suitable for “vector” operations
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Figure 5.21 A SIMD Parallel Processing System
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MIMD architecture
Multiple instruction/Multiple data
Multiple processors running in parallel
Each processor performs its own operations on its own data Processors communicate with each other
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Figure 5.22 Model of MIMD Parallel Processing
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Focus on how to design and build computer systems
Chapter 4
Binary codes
Transistors
Gates
Circuits
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Chapter 5
Von Neumann architecture Shortcomings of the sequential model of computing Parallel computers
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Computer organization examines different subsystems of a computer: memory, input/output, arithmetic/logic unit, and control unit Machine language gives codes for each primitive instruction the computer can perform, and its arguments Von Neumann machine: sequential execution of stored program Parallel computers improve speed by doing multiple tasks at one time
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