COA MCQ UNIT-4-1 - notes PDF

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Memory Locations and Addresses 1. The smallest entity of memory is called as _______ . a) Cell b) Block c) Instance d) Unit Answer:a 2. The collection of the above mentioned entities where data is stored is called as ______ . a) Block B) Set c) Word d) Byte Answer:c 3. An 24 bit address generates an address space of ______ locations . a) 1024 b) 4096 c) 2 ^ 48 d) 16,777,216 Answer:d 4. If a system is 64 bit machine , then the length of each word will be ____ . a) 4 bytes b) 8 bytes c) 16 bytes d) 12 bytes Answer:b 5. The type of memory assignment used in Intel processors is _____ . a) Little Endian b) Big Endian

c) Medium Endian d) None of the above Answer:a 6. When using the Big Indian assignment to store a number, the sign bit of the number is stored in _____ . a) The higher order byte of the word b) The lower order byte of the word c) Can’t say d) None of the above Answer:a 7. To get the physical address from the logical address generated by CPU we use ____ . a) MAR b) MMU c) Overlays d) TLB Answer:b 8. _____ method is used to map logical addresses of variable length onto physical memory. a) Paging b) Overlays c) Segmentation d) Paging with segmentation Answer:c

9. During transfer of data between the processor and memory we use ______ . a) Cache b) TLB C) Buffers d) Registers Answer: d 10. Physical memory is divided into sets of finite size called as ______ . a) Frames

b) Pages c) Blocks d) Vectors Answer: a

“Direct Memory Access”. 1. The DMA differs from the interrupt mode by a) The involvement of the processor for the operation b) The method accessing the I/O devices c) The amount of data transfer possible d) Both a and c Answer:d 2. The DMA transfers are performed by a control circuit called as a) Device interface b) DMA controller c) Data controller d) Overlooker Answer:b 3. In DMA transfers, the required signals and addresses are given by the a) Processor b) Device drivers c) DMA controllers d) The program itself Answer:c 4. After the complition of the DMA transfer the processor is notified by a) Acknowledge signal b) Interrupt signal c) WMFC signal d) None of the above Answer:b 5. The DMA controller has _______ registers

a) 4 b) 2 c) 3 d) 1 Answer:c 6. When the R/W bit of the status register of the DMA controller is set to 1, a) Read operation is performed b) Write operation is performed Answer:a 7. The controller is connected to the ____ a) Processor BUS b) System BUS c) External BUS d) None of the above Answer:b

8. Can a single DMA controller perform operations on two different disks simulteneously…?? a) True b) False Answer:a 9. The techinique whereby the DMA controller steals the access cycles of the processor to operate is called a) Fast conning b) Memory Con c) Cycle stealing d) Memory stealing Answer:c 10. The technique where the controller is given complete access to main memory is a) Cycle stealing b) Memory stealing c) Memory Con d) Burst mode

Answer:d 11. The controller uses _____ to help with the transfers when handling network interfaces. a) Input Buffer storage b) Signal echancers c) Bridge circuits d) All of the above Answer:a 12. To overcome the conflict over the possession of the BUS we use ______ a) Optimizers b) BUS arbitrators c) Multiple BUS structure d) None of the above Answer:b 13. The registers of the controller are ______ a) 64 bits b) 24 bits c) 32 bits d) 16 bits Answer:c

14. When process requests for a DMA transfer , a) Then the process is temporarily suspended b) The process continues execution c) Another process gets executed d) Both a and c Answer:d 15. The DMA transfer is initiated by _____ a) Processor b) The process being executed c) I/O devices d) OS

Answer:c

Memory Operations and Management 1. Add #%01011101,R1 , when this instruction is executed then, a) The binary addition between the operands takes place b) The Numerical value represented by the binary value is added to the value of R1 c) The addition doesn’t take place , whereas this is similar to a MOV instruction d) None of the above Answer:a 2. If we want to perform memory or arithmetic operations on data in Hexa-decimal mode then we use ___ symbol before the operand . a) ~ b) ! c) $ d) * Answer:c 3. When generating physical addresses from logical address the offset is stored in _____ . a) Translation look-aside buffer b) Relocation register c) Page table d) Shift register Answer:b 4. The technique used to store programs larger than the memory is ______ . a) Overlays b) Extension registers c) Buffers d) Both b and c Answer: a

5. The unit which acts as an intermediate agent between memory and backing store to reduce process time is _____ . a) TLB’s b) Registers c) Page tables d) Cache Answer: d 6. The Load instruction does the following operation/s, a) Loads the contents of a disc onto a memory location b) Loads the contents of a location onto the accumulators c) Load the contents of the PCB onto the register d) Both a and c Answer:b 7. Complete the following analogy :- Registers are to RAM’s as Cache’s are to _____ . a) System stacks b) Overlays c) Page Table d) TLB Answer:d 8. The BOOT sector files of the system are stored in _____ . a) Harddisk b) ROM c) RAM d) Fast solid state chips in the motherboard Answer:b 9. The transfer of large chunks of data with the involvement of the processor is done by _______ . a) DMA controller b) Arbitrator c) User system programs d) None of the above Answer:a

10. Which of the following technique/s used to effectively utilize main memory ? a) Address binding b) Dynamic linking c) Dynamic loading d) Both b and c Answer:c

Heirarchy Of Memory 1. The standard SRAM chips are costly as a) They use highly advanced micro-electronic devices. b) They house 6 transistor per chip. c) They require specially designed PCB’s. d) None of the above. Answer:b

2. The drawback of building a large memory with DRAM is a) The large cost factor. b) The inefficient memory organisation. c) The Slow speed of operation. d) All of the above.

Answer:c

3. To overcome the slow operating speeds of the secondary memory we make use of faster flash drives. a) True b) False Answer:a 4. The fastest data access is provided using _______.

a) Caches b) DRAM’s c) SRAM’s d) Registers Answer:d 5. The memory which is used to store the copy of data or instructions stored in larger memories, inside the CPU is called _______. a) Level 1 cache b) Level 2 cache c) Registers d) TLB

Answer:a

6. The larger memory placed between the primary cache and the memory is called ______. a) Level 1 cache b) Level 2 cache c) EEPROM d) TLB Answer:b 7. The next level of memory hierarchy after the L2 cache is _______. a) Secondary storage b) TLB c) Main memory d) Register Answer:d 8. The last on the hierarchy scale of memory devices is ______. a) Main memory b) Secondary memory c) TLB d) Flash drives Answer:b

9. In the memory hierarchy, as the speed of operation increases the memory size also increases. a) True b) False Answer:b

10. If we use the flash drives instead of the harddisks, then the secondary storage can go above primary memory in the hierarchy. a) True b) False Answer:b

Cache 1. The reason for the implementation of the cache memory is a) To increase the internal memory of the system b) The difference in speeds of operation of the processor and memory c) To reduce the memory access and cycle time d) All of the above Answer:b

2. The effectiveness of the cache memory is based on the property of ________. a) Locality of reference b) Memory localisation c) Memory size d) None of the above Answer:a 3. The temporal aspect of the locality of reference means a) That the recently executed instruction wont be executed soon b) That the recently executed instruction is temporarily not referenced c) That the recently executed instruction will be executed soon again d) None of the above

Answer:c 4. The spatial aspect of the locality of reference means a) That the recently executed instruction is executed again next b) That the recently executed wont be executed again c) That the instruction executed will be executed at a later time d) That the instruction in close proximity of the instruction executed will be executed in future Answer:d 5. The correspondence between the main memory blocks and those in the cache is given by _________. a) Hash function b) Mapping function c) Locale function d) Assign function

Answer:b 6. The algorithm to remove and place new contents into the cache is called _______. a) Replacement algorithm b) Renewal algorithm c) Updation d) None of the above Answer:a

7. The write-through procedure is used a) To write onto the memory directly b) To write and read from memory simultaneously c) To write directly on the memory and the cache simultaneously d) None of the above Answer:c

8. The bit used to signify that the cache location is updated is ________. a) Dirty bit b) Update bit c) Reference bit d) Flag bit Answer:a

9. The copy-back protocol is used a) To copy the contents of the memory onto the cache b) To update the contents of the memory from the cache c) To remove the contents of the cache and push it on to the memory d) None of the above

Answer:b

10. The approach where the memory contents are transfered directly to the processor from the memory is called ______. a) Read-later b) Read-through c) Early-start d) None of the above Answer:c

Mapping Functions 1. The memory blocks are mapped on to the cache with the help of ______. a) Hash functions b) Vectors c) Mapping functions d) None of the above Answer:c

2. During a write operation if the required block is not present in the cache then ______ occurs. a) Write latency b) Write hit c) Write delay d) Write miss Answer:d 3. In ________ protocol the information is directly written into main memory. a) Write through b) Write back c) Write first d) None of the above Answer:a 4. The only draw back of using the early start protocol is _______. a) Time delay b) Complexity of circuit c) Latency d) High miss rate Answer:b 5. The method of mapping the consecutive memory blocks to consecutive cache blocks is called ______. a) Set associative b) Associative c) Direct d) Indirect Answer:c 6. While using the direct mapping technique, in a 16 bit system the higher order 5 bits is used for ________. a) Tag b) Block c) Word d) Id

Answer:a 7. In direct mapping the presence of the block in memory is checked with the help of block field. a) True b) False Answer:b 8. In associative mapping, in a 16 bit system the tag field has ______ bits. a) 12 b) 8 c) 9 d) 10 Answer:a 9. The associative mapping is costlier than direct mapping. a) True b) False Answer:a 10. The technique of searching for a block by going through all the tags is ______. a) Linear search b) Binary search c) Associative search d) None of the above Answer:c

11. The set associative map technique is a combination of the direct and associative technique. a) True b) False Answer:a

Cache Miss and Hit 1. The main memory is structured into modules each with its own address register called ______. a) ABR b) TLB c) PC d) IR Answer:a

2. When consecutive memory locations are accessed only one module is accessed at a time. a) True b) False Answer:a

3. In memory interleaving, the lower order bits of the address is used to a) Get the data b) Get the address of the module c) Get the address of the data within the module d) None of the above Answer:b

4. The number successful accesses to memory stated as a fraction is called as _____. a) Hit rate b) Miss rate c) Success rate d) Access rate Answer:a

5. The number failed attempts to access memory, stated in the form of fraction is called as _________. a) Hit rate b) Miss rate c) Failure rate d) Delay rate Answer:b

6. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one,when _____ occurs. a) Delay b) Miss c) Hit d) Delayed hit Answer:b

7. In LRU, the refrenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in case of ______. a) Hit b) Miss c) Delay d) None of the above Answer:a 8. If hit rates are well below 0.9, then they’re called as speedy computers. a) True b) False Answer:b

9. The extra time needed to bring the data into memory in case of a miss is called as _____. a) Delay

b) Propagation time c) Miss penalty d) None of the above Answer:c

10. The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy. a) True b) False Answer:a

“Virtual Memory”. 1. The physical memory is not as large as the address space spanned by the processor. a) True b) False Answer:a This is one of the main reasons for the usage of virtual memories.

2. The program is divided into operable parts called as _________. a) Frames b) Segments c) Pages d) Sheets Answer:b 3. The techniques which move the program blocks to or from the physical memory is called as ______. a) Paging b) Virtual memory organisation c) Overlays d) Framing

Answer:b

4. The binary address issued to data or instructions are called as ______. a) Physical address b) Location c) Relocatable address d) Logical address Answer:d

5. __________is used to implement virtual memory organisation. a) Page table b) Frame table c) MMU d) None of the above Answer:c The MMU stands for Memory Management Unit.

6. ______ translates logical address into physical address. a) MMU b) Translator c) Compiler d) Linker Answer:a The MMU translates the logical address into physical address by adding an offset.

7. The main aim of virtual memory organisation is a) To provide effective memory access. b) To provide better memory transfer. c) To improve the execution of the program. d) All of the above.

Answer:d

8. The DMA doesn’t make use of the MMU for bulk data transfers. a) True b) False Answer:b The DMA stands for Direct Memory Access,in which a block of data gets directly transferred from the memory.

9. The virtual memory basically stores the next segment of data to be executed on the _________. a) Secondary storage b) Disks c) RAM d) ROM

Answer:a 10. The asscociatively mapped virtual memory makes use of _______. a) TLB b) Page table c) Frame table d) None of the above Answer:a TLB stands for Translation Look-aside Buffer.

Accessing I/O Devices 1. In memory-mapped I/O… a) The I/O devices and the memory share the same address space b) The I/O devices have a seperate address space c) The memory and I/O devices have an associated address space d) A part of the memory is specifically set aside for the I/O operation Answer:a

2. The usual BUS structure used to connect the I/O devices is a) Star BUS structure b) Multiple BUS structure c) Single BUS structure d) Node to Node BUS structure Answer:c 3. In intel’s IA-32 architecture there is a seperate 16 bit address space for the I/O devices..?? a) False b) True Answer:b 4. The advantage of I/O mapped devices to memory mapped is a) The former offers faster transfer of data b) The devices connected using I/O mapping have a bigger buffer space c) The devices have to deal with fewer address lines d) No advantage as such Answer:c 5. The system is notified of a read or write operation by a) Appending an extra bit of the address b) Enabling the read or write bits of the devices c) Raising an appropriate interrupt signal d) sending a special signal along the BUS Answer:d 6. To overcome the lag in the operating speeds of the I/O device and the processor we use a) BUffer spaces b) Status flags c) Interrupt signals d) Exceptions Answer:b 7. The method of accessing the I/O devices by repeatedly checking the status flags is a) Program-controlled I/O b) Memory-mapped I/O c) I/O mapped

d) None Answer:a 8. The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is a) Exceptions b) Signal handling c) Interrupts d) DMA Answer:c 9. The method which offers higher speeds of I/O transfers is a) Interrupts b) Memory mapping c) Program-controlled I/O d) DMA Answer:d 10. The process where in the processor constantly checks the status flags is called as a) Polling b) Inspection c) Reviewing d) Echoing Answer:a

1. What characteristic of RAM memory makes it not suitable for permanent storage? (A) too slow (B) unreliable (C) it is volatile (D) too bulky Ans: C

2. The idea of cache memory is based (A) on the property of locality of reference (B) on the heuristic 90-10 rule (B) on the fact that references generally tend to cluster (D) all of the above Ans: A 3. Which of the following is lowest in memory hierarchy? (A) Cache memory (B) Secondary memory (C) Registers (D) RAM (E) None of these Ans (B) Secondary memory

4. If memory access takes 20 ns with cache and 110 ns with out it, then the ratio ( cache uses a 10 ns memory) is (A) 93% (B) 90% (C) 88% (D) 87% Ans: B 5. In a memory-mapped I/O system, which of the following will not be there? (A) LDA (B) IN (C) ADD (D) OUT Ans: A

6.

Cache memory acts between (A) CPU and RAM (B) RAM and ROM (C) CPU and Hard Disk (D) None of these Ans: A 7. Write Through technique is used in which memory for updating the data

(A) Virtual memory (B) Main memory (B) Auxiliary memory (D) Cache memory Ans: D 8. Generally Dynamic RAM is used as main memory in a computer system as it (A) Consumes less power (B) has higher speed (B) has lower cell density (D) needs refreshing circuitary Ans: B

9.

Virtual memory consists of (A) Static RAM (B) Dynamic RAM (B) Magnetic memory (D) None of these Ans: A

10. If the main memory is of 8K bytes and the cache memory is of 2K words. It uses associative mapping. Then each word of cache memory shall be (A) 11 bits (B) 21 bits (C) 16 bits (D) 20 bits Ans: C 11. Cache memory works on the principle of (A) Locality of data (B) Locality of memory (B) Locality of reference (D) Locality of reference & memory Ans: C

12. The main memory in a Personal Computer (PC) is made of (A) cache memory. (B) static RAM (B) Dynamic Ram (D) both (A) and (B) . Ans: D 13. Memory unit accessed by content is called (A) Read only memory (B) Programmable Memory (B) Virtual Memory (D) Associative Memory Ans: D 14. An interface that provides a method for transferring binary information between internal storage and external devices is called (A) I/O interface (B) Input interface (C) Output interface (D) I/O bus Ans: A 15. An interface that provides a method for transferring binary information between internal storage and external devices is called (A) I/O interface (B) Input interface (C) Output interface (D) I/O bus Ans: A 16. Status bit is also called (A) Binary bit (B) Flag bit (C) Signed bit (D) Unsigned bit Ans: B 17. An address in main memory is called (A) Physical address (B) Logical address (C) Memory address (D) Word address Ans: A 18. The performance of cache memory is frequently measured in terms of a quantity called (A) Miss ratio. (B) Hit ratio. (C) Latency ratio. (D) Read ratio. Ans: C 19. An interface that provides I/O transfer of data directly to and form the memory unit and peripheral is termed as (A) DDA. (B) Serial interface. (C) BR. (D) DMA. Ans: D 20. Which of the following is a main memory (A) Secondary memory. (B) Auxiliary memory. (B) Cache memory. (D) Virtual memory. Ans: C 21. The memory unit that communicates directly with the CPU is called the (A) main memory (B) Secondary memory (B) shared memory (D) auxiliary memory. Ans: A 22. The average time required to reach a storage location in memory and obtain its contents is called (A) Latency time. (B) Access time. (B) Turnaround time. (D) Response time. Ans: B

23. A page fault (A) Occurs when there is an ...