[COAL] Assignment 1 - SAP1 Architecture PDF

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Assignment in Computer Architecture and Assembly Language class...

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Garcia, Divine Dacones BSCS 3-4 Computer Systems Organization and Assembly Language Assignment 1: SAP1 Architecture 1. What is SAP1 Architecture? (Explain in your own words)

SAP1 stands for Simple as Possible and from that you can know that a computer with this architecture is basic. Despite of its simplicity, it covers various advanced concepts. It is primarily used for providing an understanding as to how the microprocessor interacts with the components in the system such as memory. It can only perform arithmetic operations such as addition and subtraction. It is an 8 bit type of architecture and has 16 x 8 memory meaning in each memory location there are 8 bits thus need 4 address lines may come from the Program Counter during computer run phase or from the 4 address switches during the program phase.

2. Draw the SAP1 Architecture. Cp

8

Program Counter

Ep

4

8

Accumulator CLK A 8

4

Input & MAR

CLK

4

8

W bus

4

8

8

16x8 RAM

Adder/ Subtracter

8

B Register

CLK

8

Instruction Register

Ei

8 4

Output Register

4

ControllerSequencer 12

8

CLK

Binary Display CLR

CLK

3. Define all the components of SAP1?

The components of SAP1 are Program Counter, Input and Memory Address Register, RAM, Instruction Register, Controller-Sequencer, Adder/Subtractor, Accumulator A, B-Register, Output Register, Binary Display. The program counter is responsible for communicating the memory address of next instruction which is composed of 4 bit to be retrieved and executed – acting like a pointer register. The memory address register (MAR) stores the address of the data and the instruction to be executed from the program counter through the W bus. Later on, the 4 bit address will be applied to the RAM. The random access memory (RAM) is a16x8 static TTL meaning in each 16 memory location there is 8-bit data or instruction. It receives the 4 bit address during the computer run and when the read operation is done, the instruction in the RAM will be placed on W bus for the use of other components in the computer. The instruction register stores the instruction when it is placed at the W bus on the next positive clock edge. It contains 2 nibble, the upper one being a two state output going to the controller-sequencer while the lower one is three state output read onto the W bus when necessary. The controller- sequencer regulates the control signal for each block in order for the desired sequence of actions to be done in a 12 bit word format. The CLR signal returns the computer to its original state before each operation. The word generated reveals how the registers will function to the next positive clock (CLK) edge. The adder/subtractor uses 2s complement so when the input is 0 (low) the formula will be S = A + B but when the input is 1 (high) the formula will be S = A + B’ + 1. It is asynchronous thus its contents also change as the input changes. These contents appear on the W bus when is 1 (high). The accumulator A stores the first number to be added or subtracted. It has two outputs – the one going to the adder/subtractor and the other one to the W bus through tri-state buffer. The sum or the difference of both numbers will be stored here if the value of is 0 (low). On the other hand, if the value of is 1 (high), the value will appear on the W bus which can then be read by the output register. The B register stores the second number to be added or subtracted from the accumulator A to the adder/subtractor. It loads the data when it is available at W bus and is 0 (low). The output register hold the answer for the instruction. The answer is loaded here through the W bus when in the next positive clock edge, the is 1 (high) and is 0 (low). The answer can be displayed through the LED. The binary display is a row of 8 LEDs showing the contents of the output register.

4. What is the Machine Code of the following arithmetic operations? 2+20-6+4-23

Address

Contents

Machine Code

0H

LDA 9H

0000 1001

1H

ADD AH

0001 1010

2H

SUB BH

0010 1011

3H

ADD CH

0001 1100

4H

SUB DH

0010 1101

5H

OUT

1110 XXXX

6H

HLT

1111 XXXX

7H

XX

XXXX XXXX

8H

XX

XXXX XXXX

9H

2H

0000 0010

AH

14H

0001 0100

BH

6H

0000 0110

CH

4H

0000 0100

DH

17H

0001 0111

References Chishti, R. (25 April 2015). Sap 1. Retrieved from https://www.slideshare.net/Jawad_Ahmad/sap-147400149 Bhujel,

D. (December 2015). SAP-1 Architecture. https://deeprajbhujel.blogspot.com/2015/12/sap-1-architecture.html

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