Digital Clock using Sequential Logic PDF

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Summary

Sequential Circuits are basically simple circuits with feedback. It uses logic
gates to provide the control functions, and it uses flip-flops to store the digital
signals. Sequential circuits are the basis for building “memory” into logic circuits where they depend on the past informatio...

Description

Sequential Logic Design for a Digital Clock

Submitted to ENGR. RODRIGO S. PANGANTIHON, JR., MIT, MSCpE Professor in EE 538/L

In Partial Fulfilment of the Course Requirements in EE 538/L – Logic Circuits and Switching Theory 5:30PM-7:30PM

Submitted by CHRISTINE ANN MISANES Student

October 26,2018

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INTRODUCTION Sequential Circuits are basically simple circuits with feedback. It uses logic gates to provide the control functions, and it uses flip-flops to store the digital signals. Sequential circuits are basis for building “memory” into logic circuits where they depend on the past information where the output values of a sequential circuit depend on the temporal sequence of input values. Digital clock simply consists 3 sets of counters, the seconds, the minutes, and hours. The use of a 7-segment decoder, 555 timer, and JK Flip-flop IC’s are needed to implement the digital clock. A 12-hour digital displaying HH.MM.SS will be its output.

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OBJECTIVES The objectives of this plate are as follows: 1. To design a digital clock using sequential logic design. 2. To execute simulation before implementation. 3. To place the components on the breadboard and connect to corresponding pinouts/connections. 4. To operate the device displaying seconds as 00-59, minutes as 00-59, and hours as 00-12 .

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LIST OF MATERIALS

Materials used in this plate are listed below: No.

Material

Quantity

Specification

1.

7-segment display

6 pieces

Common Cathode

2.

74LS08

3 pieces

Quad-Output, Two-Input AND gate

3.

74LS32

4 pieces

Quad-Output, Two-Input OR gate

4.

74LS73

11 pieces

JK-Flipflop

5.

CD4511

6 pieces

Decoder

6.

555 timer

1 piece

7.

Electrolytic Capacitor

1 piece

10µF(25V);

8.

Resistor

6 pieces

1kΩ (1/2 W);

9.

Potentiometer

1 piece

10kΩ

10.

Tact Switch

5 pieces

2-Legged Button

IV – EXPERIMENTAL PROCEDURES To actualize this design, the following laboratory procedures were taken: 1. Determine the specific logic circuit to be used. 2. Provide the necessary equations to perform the output. 3. Use K-Mapping (Karnaugh Mapping) to simplify equations. 4. Apply De Morgan’s Theorem to minimize the number of IC’s. 5. Simulation using Logisim or Proteus. 6. Placing the components on the breadboard and connect the wires. V – PROBLEM ANALYSIS

VI – LOGIC CIRCUIT / DIAGRAM COUNTER

DIGITAL CLOCK

VIII – CONCLUSIONS In light of this design, the following conclusions were drawn: 1) Connecting the components on the breadboard requires patience, Determination and proper understanding. 2) Checking the breadboard and IC’s are necessary to avoid delays. 3) Non-overlapping wires can contribute easier troubleshooting. 4) Mapping helps in easier troubleshooting also. 5) JK Flip-flops are very sensitive.

IX – RECOMMENDATIONS After the implementation of this project, the following recommendations were offered: 1)

Equations must be reduced in order to come up with simpler equations.

2)

Use Karnaugh Map and De Morgan’s theorem .

3)

The power supply must have enough amperage and voltage to cater the circuit.

4)

Place the IC’s 3-4 holes apart for neater wiring and for easier troubleshooting.

5)

Be sure to have clean and proper wiring to have a clearer path for tracking the flow of the circuit and have a correct output.

X – REFERENCES https://www.seas.upenn.edu/~cit595/cit595s10/lectures/seqcircuitsPart1.pdf https://courses.cs.washington.edu/courses/cse370/03au/lectures/06-Seq.pdf https://www.oreilly.com/library/view/introduction-to-digital/9780470900550/chap8sec002.html https://link.springer.com/chapter/10.1007/978-1-4613-0047-2_5 http://ecelabs.njit.edu/ece394/lab3.php

XI – PROOF OF IMPLEMENTATION...