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Functional Unit

1. The ______ format is usually used to store data. a) BCD b) Decimal c) Hexadecimal d) Octal View Answer Answer: a Explanation: The data usually used by computers have to be stored and represented in a particular format for ease of use. 2. The 8-bit encoding format used to store data in a computer is ______ a) ASCII b) EBCDIC c) ANCI d) USCII View Answer Answer: b Explanation: The data to be stored in the computers have to be encoded in a particular way so as to provide secure processing of the data. 3. A source program is usually in _______ a) Assembly language b) Machine level language c) High-level language d) Natural language View Answer Answer: c Explanation: The program written and before being compiled or assembled is called as a source program. 4. Which memory device is generally made of semiconductors? a) RAM b) Hard-disk c) Floppy disk d) Cd disk View Answer Answer: a Explanation: Memory devices are usually made of semiconductors for faster manipulation of the contents. 5. The small extremely fast, RAM’s are called as _______ a) Cache b) Heaps c) Accumulators d) Stacks View Answer Answer: a Explanation: These small and fast memory devices are compared to RAM because they optimize the performance of the system and they only keep files which are required by the current process in them 6. The ALU makes use of _______ to store the intermediate results. a) Accumulators b) Registers c) Heap d) Stack View Answer Answer: a Explanation: The ALU is the computational center of the CPU. It performs all mathematical and logical operations. In order to perform better, it uses some internal memory spaces to store immediate results. 7. The control unit controls other units by generating ___________ a) Control signals b) Timing signals c) Transfer signals d) Command Signals View Answer Answer: b Explanation: This unit is used to control and coordinate between the various parts and components of the CPU. 8. ______ are numbers and encoded characters, generally used as operands. a) Input b) Data c) Information d) Stored Values View Answer Answer: b Explanation: None. 9. The Input devices can send information to the processor. a) When the SIN status flag is set b) When the data arrives regardless of the SIN flag c) Neither of the cases d) Either of the cases View Answer Answer: a Explanation: The input devices use buffers to store the data received and when the buffer has some data it sends it to the processor. 10. ______ bus structure is usually used to connect I/O devices. a) Single bus b) Multiple bus c) Star bus d) Rambus View Answer Answer: a Explanation: BUS is a bunch of wires which carry address, control signals and data. It is used to connect various components of the computer

Bus Structure

1. The main virtue for using single Bus structure is ____________ a) Fast data transfers b) Cost effective connectivity and speed c) Cost effective connectivity and ease of attaching peripheral devices d) None of the mentioned View Answer Answer: c Explanation: By using a single BUS structure we can minimize the amount of hardware (wire) required and thereby reducing the cost. 2. ______ are used to overcome the difference in data transfer speeds of various devices. a) Speed enhancing circuitory b) Bridge circuits c) Multiple Buses d) Buffer registers View Answer Answer: d Explanation: By using Buffer registers, the processor sends the data to the I/O device at the processor speed and the data gets stored in the buffer. After that the data gets sent to or from the buffer to the devices at the device speed. 3. To extend the connectivity of the processor bus we use ________ a) PCI bus b) SCSI bus c) Controllers d) Multiple bus View Answer Answer: a Explanation:

PCI BUS is used to connect other peripheral devices that require a direct connection with the processor. 4. IBM developed a bus standard for their line of computers ‘PC AT’ called _____ a) IB bus b) M-bus c) ISA d) None of the mentioned View Answer Answer: c Explanation: None. 5. The bus used to connect the monitor to the CPU is ______ a) PCI bus b) SCSI bus c) Memory bus d) Rambus View Answer Answer: b Explanation: SCSI BUS is usually used to connect video devices to the processor. 6. ANSI stands for __________ a) American National Standards Institute b) American National Standard Interface c) American Network Standard Interfacing d) American Network Security Interrupt View Answer Answer: a Explanation: None. 7. _____ register Connected to the Processor bus is a single-way transfer capable. a) PC b) IR c) Temp d) Z View Answer Answer: d Explanation: The Z register is a special register which can interact with the processor BUS only. 8. In multiple Bus organisation, the registers are collectively placed and referred as ______ a) Set registers b) Register file c) Register Block d) Map registers View Answer Answer: b Explanation: None. 9. The main advantage of multiple bus organisation over a single bus is _____ a) Reduction in the number of cycles for execution b) Increase in size of the registers c) Better Connectivity d) None of the mentioned View Answer Answer: a Explanation: None. 10. The ISA standard Buses are used to connect ___________ a) RAM and processor b) GPU and processor c) Harddisk and Processor d) CD/DVD drives and Processor View Answer Answer: c Explanation: None.

Addressing Mode

1. The instruction, Add #45,R1 does _______ a) Adds the value of 45 to the address of R1 and stores 45 in that address b) Adds 45 to the value of R1 and stores it in R1 c) Finds the memory location 45 and adds that content to that of R1 d) None of the mentioned View Answer Answer: b Explanation: The instruction is using immediate addressing mode hence the value is stored in the location 45 is added. 2. In the case of, Zero-address instruction method the operands are stored in _____ a) Registers b) Accumulators c) Push down stack d) Cache View Answer Answer: c Explanation: In this case, the operands are implicitly loaded onto the ALU. 3. Add #45, when this instruction is executed the following happen/s _______ a) The processor raises an error and requests for one more operand b) The value stored in memory location 45 is retrieved and one more operand is requested c) The value 45 gets added to the value on the stack and is pushed onto the stack d) None of the mentioned View Answer Answer: b Explanation: None. 4. The addressing mode which makes use of in-direction pointers is ______ a) Indirect addressing mode b) Index addressing mode c) Relative addressing mode d) Offset addressing mode View Answer Answer: a Explanation: In this addressing mode, the value of the register serves as another memory location and hence we use pointers to get the data. 5. In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is ______ a) EA = 5+R1 b) EA = R1 c) EA = [R1] d) EA = 5+[R1] View Answer Answer: d Explanation: This instruction is in Base with offset addressing mode.

Accessing I/O

1. In memory-mapped I/O ____________ a) The I/O devices and the memory share the same address space b) The I/O devices have a separate address space c) The memory and I/O devices have an associated address space d) A part of the memory is specifically set aside for the I/O operation

View Answer Answer: a Explanation: Its the different modes of accessing the i/o devices. 2. The usual BUS structure used to connect the I/O devices is ___________ a) Star BUS structure b) Multiple BUS structure c) Single BUS structure d) Node to Node BUS structure View Answer Answer: c Explanation: BUS is a collection of address, control and data lines used to connect the various devices of the computer. 3. In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices. a) False b) True View Answer Answer: b Explanation: This type of access is called as I/O mapped devices. 4. The advantage of I/O mapped devices to memory mapped is ___________ a) The former offers faster transfer of data b) The devices connected using I/O mapping have a bigger buffer space c) The devices have to deal with fewer address lines d) No advantage as such View Answer Answer: c Explanation: Since the I/O mapped devices have a separate address space the address lines are limited by the amount of the space allocated. 5. The system is notified of a read or write operation by ___________ a) Appending an extra bit of the address b) Enabling the read or write bits of the devices c) Raising an appropriate interrupt signal d) Sending a special signal along the BUS View Answer Answer: d Explanation: It is necessary for the processor to send a signal intimating the request as either read or write. 6. To overcome the lag in the operating speeds of the I/O device and the processor we use ___________ a) BUffer spaces b) Status flags c) Interrupt signals d) Exceptions View Answer Answer: b Explanation: The processor operating is much faster than that of the I/O devices, so by using the status flags the processor need not wait till the I/O operation is done. It can continue with its work until the status flag is set. 7. The method of accessing the I/O devices by repeatedly checking the status flags is ___________ a) Program-controlled I/O b) Memory-mapped I/O c) I/O mapped d) None of the mentioned View Answer Answer: a Explanation: In this method, the processor constantly checks the status flags, and when it finds that the flag is set it performs the appropriate operation. 8. The method of synchronising the processor with the I/O device in which the device sends a signal when it is ready is? a) Exceptions b) Signal handling c) Interrupts d) DMA View Answer Answer: c Explanation: This is a method of accessing the I/O devices which gives the complete power to the devices, enabling them to intimate the processor when they’re ready for transfer. 9. The method which offers higher speeds of I/O transfers is ___________ a) Interrupts b) Memory mapping c) Program-controlled I/O d) DMA View Answer Answer: d Explanation: In DMA the I/O devices are directly allowed to interact with the memory without the intervention of the processor and the transfers take place in the form of blocks increasing the speed of operation. 10. The process wherein the processor constantly checks the status flags is called as ___________ a) Polling b) Inspection c) Reviewing d) Echoing View Answer Answer: a Explanation: None.

Interrupt

1. The interrupt-request line is a part of the ___________ a) Data line b) Control line c) Address line d) None of the mentioned View Answer Answer: b Explanation: The Interrupt-request line is a control line along which the device is allowed to send the interrupt signal. 2. The return address from the interrupt-service routine is stored on the ___________ a) System heap b) Processor register c) Processor stack d) Memory View Answer Answer: c Explanation: The Processor after servicing the interrupts as to load the address of the previous process and this address is stored in the stack. 3. The signal sent to the device from the processor to the device after receiving an interrupt is ___________ a) Interrupt-acknowledge b) Return signal c) Service signal d) Permission signal View Answer Answer: a Explanation: The Processor upon receiving the interrupt should let the device know that its request is received. 4. When the process is returned after an interrupt service ______ should be loaded again. i) Register contents ii) Condition codes iii) Stack contents iv) Return

addresses a) i, iv b) ii, iii and iv c) iii, iv d) i, ii View Answer Answer: d Explanation: None. 5. The time between the receiver of an interrupt and its service is ______ a) Interrupt delay b) Interrupt latency c) Cycle time d) Switching time View Answer Answer: b Explanation: The delay in servicing of an interrupt happens due to the time is taken for contact switch to take place. 6. Interrupts form an important part of _____ systems. a) Batch processing b) Multitasking c) Real-time processing d) Multi-user View Answer Answer: c Explanation: This forms an important part of the Real time system since if a process arrives with greater priority then it raises an interrupt and the other process is stopped and the interrupt will be serviced

Synchronous Bus

1. The primary function of the BUS is __________ a) To connect the various devices to the cpu b) To provide a path for communication between the processor and other devices c) To facilitate data transfer between various devices d) All of the mentioned View Answer Answer: a Explanation: The BUS is used to allow the passage of commands and data between cpu and devices. 2. The classification of BUSes into synchronous and asynchronous is based on __________ a) The devices connected to them b) The type of data transfer c) The Timing of data transfers d) None of the mentioned View Answer Answer: c Explanation: The BUS is classified into different types for the convenience of use and depending on the device. 3. The device which starts data transfer is called __________ a) Master b) Transactor c) Distributor d) Initiator View Answer Answer: d Explanation: The device which starts the data transfer is called an initiator. 4. The device which interacts with the initiator is __________ a) Slave b) Master c) Responder d) Friend View Answer Answer: a Explanation: The device which receives the commands from the initiator for data transfer. 5. In synchronous BUS, the devices get the timing signals from __________ a) Timing generator in the device b) A common clock line c) Timing signals are not used at all d) None of the mentioned View Answer Answer: b Explanation: The devices receive their timing signals from the clock line of the BUS. 6. The delays caused in the switching of the timing signals is due to __________ a) Memory access time b) WMFC c) Propagation delay d) Processor delay View Answer Answer: c Explanation: The time taken for the signal to reach the BUS from the device or the circuit accounts for this delay.

Asynchronous DRAM

1. The Reason for the disregarding of the SRAM’s is ________ a) Low Efficiency b) High power consumption c) High Cost d) All of the mentioned View Answer Answer: c Explanation: The reason for the high cost of the SRAM is because of the usage of more number of transistors. 2. The disadvantage of DRAM over SRAM is/are _______ a) Lower data storage capacities b) Higher heat dissipation c) The cells are not static d) All of the mentioned View Answer Answer: c Explanation: This means that the cells won’t hold their state indefinitely. 3. The reason for the cells to lose their state over time is ________ a) The lower voltage levels b) Usage of capacitors to store the charge c) Use of Shift registers d) None of the mentioned View Answer Answer: b Explanation: Since capacitors are used the charge dissipates over time. 4. The capacitors lose the charge over time due to ________ a) The leakage resistance of the capacitor b) The small current in the transistor after being turned on c) The defect of the capacitor d) None of the mentioned View Answer Answer: a

Explanation: The capacitor loses charge due to the backward current of the transistor and due to the small resistance. 5. _________ circuit is used to restore the capacitor value. a) Sense amplify b) Signal amplifier c) Delta modulator d) None of the mentioned View Answer Answer: a Explanation: The sense amplifier detects if the value is above or below the threshold and then restores it. 6. To reduce the number of external connections required, we make use of ______ a) De-multiplexer b) Multiplexer c) Encoder d) Decoder View Answer Answer: b Explanation: We multiplex the various address lines onto fewer pins.

Pipe-lining

1. ______ have been developed specifically for pipelined systems. a) Utility software b) Speed up utilities c) Optimizing compilers d) None of the mentioned View Answer Answer: c Explanation: The compilers which are designed to remove redundant parts of the code are called as optimizing compilers. 2. The pipelining process is also called as ______ a) Superscalar operation b) Assembly line operation c) Von Neumann cycle d) None of the mentioned View Answer Answer: b Explanation: It is called so because it performs its operation at the assembly level. 3. The fetch and execution cycles are interleaved with the help of ________ a) Modification in processor architecture b) Clock c) Special unit d) Control unit View Answer Answer: b Explanation: The time cycle of the clock is adjusted to perform the interleaving. 4. Each stage in pipelining should be completed within ___________ cycle. a) 1 b) 2 c) 3 d) 4 View Answer Answer: a Explanation: The stages in the pipelining should get completed within one cycle to increase the speed of performance. 5. In pipelining the task which requires the least time is performed first. a) True b) False View Answer Answer: b Explanation: This is done to avoid starvation of the longer task. 6. If a unit completes its task before the allotted time period, then _______ a) It’ll perform some other task in the remaining time b) Its time gets reallocated to a different task c) It’ll remain idle for the remaining time d) None of the mentioned View Answer Answer: c Explanation: None. 7. To increase the speed of memory access in pipelining, we make use of _______ a) Special memory locations b) Special purpose registers c) Cache d) Buffers View Answer Answer: c Explanation: By using the cache we can reduce the speed of memory access by a factor of 10. 8. The periods of time when the unit is idle is called as _____ a) Stalls b) Bubbles c) Hazards d) Both Stalls and Bubbles View Answer Answer: d Explanation: The stalls are a type of hazards that affect a pipelined system.

Cache

1. ______ have been developed specifically for pipelined systems. a) Utility software b) Speed up utilities c) Optimizing compilers d) None of the mentioned View Answer Answer: c Explanation: The compilers which are designed to remove redundant parts of the code are called as optimizing compilers. 2. The pipelining process is also called as ______ a) Superscalar operation b) Assembly line operation c) Von Neumann cycle d) None of the mentioned View Answer Answer: b Explanation: It is called so because it performs its operation at the assembly level. 3. The fetch and execution cycles are interleaved with the help of ________ a) Modification in processor architecture b) Clock c) Special unit d) Control unit View Answer Answer: b Explanation: The time cycle of the clock is adjusted to perform the interleaving. 4. Each stage in pipelining should be completed within

___________ cycle. a) 1 b) 2 c) 3 d) 4 View Answer Answer: a Explanation: The stages in the pipelining should get completed within one cycle to increase the speed of performance. 5. In pipelining the task which requires the least time is performed first. a) True b) False View Answer Answer: b Explanation: This is done to avoid starvation of the longer task. 6. If a unit completes its task before the allotted time period, then _______ a) It’ll perform some other task in the remaining time b) Its time gets reallocated to a different task c) It’ll remain idle for the remaining time d) None of the mentioned View Answer Answer: c Explanation: None. 7. To increase the speed of memory access in pipelining, we make use of _______ a) Special memory locations b) Special purpose registers c) Cache d) Buffers View Answer Answer: c Explanation: By using the cache we can reduce the speed of memory access by a factor of 10. 8. The periods of time when the unit is idle is called as _____ a) Stalls b) Bubbles c) Hazards d) Both Stalls and Bubbles View Answer Answer: d Explanation: The stalls are a type of hazards that affect a pipelined system.

Memory Operation

1. Add #%01011101,R1 , when this instruction is executed then _________ a) The binary addition between the operands takes place b) The Numerical value represented by the binary value is added to the value of R1 c) The addition doesn’t take place, whereas this is similar to a MOV instruction d) None of the mentioned View Answer Answer: a Explanation: This performs operations in binary mode directly....