DUC DDC Design STD Diapos PDF

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Diapos clase DUC - DDC ESR. Formulas y teoría....

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DUC-DDC DESIGN

DIGITAL UP CONVERTER (DUC) Conceptual Scheme

Objectives: 1. Move the base-band signal to the transmission frequency fo. 2. Accommodate the base-band bandwidth to the transmission band.

DIGITAL UP CONVERTER (DUC) Spectrum LTE Signal

Notice that, for ESR, according figure and the selected sampling frequency fs=48000Hz the LTE base-band signal bandwidth is: BWBaseBand= (73/128)*48000Hz = 27375Hz.

Such number clearly claims for a reduction of transmitted bandwidth. The audio channel is useless beyond 20kHz.

DIGITAL UP CONVERTER (DUC) DUC Interpolation & Decimation  DUC module implements interpolation by N and decimation by D process around the low-pas filter (LPF) of each IQ branch.  This facilitates the bandwidth and sample rate adjustment by performing a global N/D interpolation.  Interpolation adds N-1 zeros between two original I or Q samples before low pas filtering. Reb(n)  Imb(n)

Ts

Ts

Tm

 Decimation eliminates, from filter output, D-1 samples from the N ones.

 The number of output samples OUT = IN·N/D, where IN is the number of input ones.

DIGITAL DOWN CONVERTER (DDC) Where v(n) is a pass-band signal allocated at fo as central frequency.

DUC/DDC INTERPOLATION DUC assumptions

fs= 48000Hz N=4 fi defines the maximum frequency of LTE bandwidth LTE 128 FFT mode: 73 non-zero carriers fi = (36/128)·48000=13500Hz With fi/4 = 3375Hz and (fs-fi)/4 = 8625Hz For LTE 128 FFT mode Uplink without PUCCH: 48 non-zero carriers fi = (24/128)·48000=9000Hz With fi/4 = 2250Hz and (fs-fi)/4 = 9750Hz

Filter design

DUC/DDC DECIMATION ecimatio

Spectrum Changes

Before decimation, filter eliminate components

Decimating D=2

DUC/DDC DECIMATION ecimatio : Time considerations

 Interpolation by 4 adds 3 zeros (red samples) in the data flow.  After filtering such red samples get the green values  At perfect synchronisation, when decimating by D=4 we eliminate (three samples out) the green samples and ‘’theoretically’’ original blue samples remain almost the same.

DUC/DDC DECIMATION ecimatio : Time considerations

 What happen when synchronisation is lost?

 We choose one (orange for example) that differs from the optimal one

Distortion would appear

Improved Decimation selection criteria 1) Averaging the N/D samples 2) Looking for the set of D samples with higher energy 3) ….?

Testing DUC/DDC Implementation Testing using reference tones Input Signal: Four tones at 1.4MHz, 1.652MHz, 270kHz and 540kHz. Each with different power levels and distributed to occupy the relative LTE bandwidth. Sampling frequency 1.92MHz.

Testing DUC/DDC Implementation Testing using reference tones

Interpolation Output. Complex signal with I and Q components. Interpolation done through zero padding plus digital filtering. Interpolation level N = 8.

Interpolating by N=60.

Testing DUC/DDC Implementation Required Filters

Interpolation level N = 8.

Testing DUC/DDC Implementation Required Filters

Interpolation level N = 60.

But using the filter designed for N=8.

Testing DUC/DDC Implementation Decimation Several tones

Interpolation level N = 6 Not filtered

Interpolation level N = 6 Filtered

Interpolation level N = 6 Filtered & decimated by 2

Interpolation level N = 6 Filtered & decimated by 3

Testing DUC/DDC Implementation Combining Interpolation N & Decimation D: N/D ratio Scenario Number of samples in a subframe NofSamplesSubF= 128·14 = 1792 If CP is added NofSamplesSubF= 1920 ESR system constraints: • Transmission bandwidth TBw=3-7kHz • DAC_JACK module only accepts 1024 each timeslot. Assuming sampling frequency fs=48000Hz Signal Base band bandwidth SBBB=(36/128)·48000Hz=13500Hz

Taking as example TBw=7kHz we need to compress the SBBB by R=13500Hz·2/7kHz=3.85 Lets assume that Interpolation/Decimation process allows to compress the bandwidth.

Lets take R = 4 (only as example)

Testing DUC/DDC Implementation Combining Interpolation N & Decimation D: N/D ratio With R=4 and without CP NofSamplesSubF=1792 (Mapping Output) Only the DUC is capable to modify the samples rate by N/D=R With R=N/D=4 the number of samples at the output of DUC, NofOUTDUC=1792·4=7168 Remind DAC_JACK only accepts 1024 samples/timeslot. We need 7168/1024=7timeslots for transmitting the samples associated to a subframe. This is a valid solution for implementation purposes. Nevertheless other exist that fits N/D=4

Testing DUC/DDC Implementation Combining Interpolation N & Decimation D: N/D ratio With R=4 and with CP NofSamplesSubF=1920 (Mapping Output) With R=N/D=4 the number of samples at the output of DUC, NofOUTDUC=1920·4=7680 Then we need 7680/1024=7.5 timeslots for transmitting the samples associated to a subframe. This is a bad value. We need to coordinate the LTE specifications and inplementation issues. A solution comes from looking for a multiple of NofOUTDUC that can be exactly divided by 1024 (number of samples that accept the DAC_JACK module) or make that 1920·P=1024·S

Testing DUC/DDC Implementation Combining Interpolation N & Decimation D: N/D ratio With R=4 and with CP P=8 and S=15 is a solution. This requires to INTERPOLATE by 8 and make the MAPPING module to deliver a subframe every 15 timeslots. But TBw reduces to 3375 Hz

Wider bandwidth facilitate to achieve higher performance One option is to use P=N/D then 1920·N/D=1024·S Assuming S=7 we get N/D=8.7/15 And N=56 and D=15 satisfy the conditions: Interpolate by 56 and Decimate by 15 With that TBw = 7232Hz

Testing DUC/DDC Implementation Combining Interpolation N & Decimation D: N/D ratio Lest continue with N=56 and D=15 to test the UDC/DDC

Doing such interpolation in one step would result in strong distortion of existing signal. Notice that DUC interpolation filter, assuming a N=56 requires a very sharp filter with a bandpass around LTE_BB_bandwidth/N = 240Hz and an stop band at (fsLTE_BB_bandwidth)/N=616 Hz (assuming fs=48kHz).

Spectrum after Interpolating by 56, filtering and decimating by 15

Testing DUC/DDC Implementation Combining Interpolation N & Decimation D: N/D ratio Moving to fOL=10kHz

Now the same result but with a set of tones of equal amplitude simulating and OFDM signal as input. Notice the distortion

Testing DUC/DDC Implementation

Checking Distortion Level: Compare to well known signals Comparison done with PSS signals (DownLink). It can be done with DMRS for UpLink

Reference PSS

PSS at DDC Output

Use the Error Vector Magnitude (EVM) measurement process to compare

Testing DUC/DDC Implementation esting DUC DDC using an easy to visualize signal

 Generate RAMP signal samples to be used as input of MAPPING module (instead of QAM symbols).

 Notice the output of MAPPING module (figure for DownLink)

MAPPING output Pattern of 1024 RAMP samples.

MAPPING input

Testing DUC/DDC Implementation esting DUC DDC using an easy to visualize signal

Generate a RAMP signal in MAPPING module to fill the data values of a LTE frame.

Below UPLINK subframe detaill showing the DMRS signal

RAMP signal values allocated in frequency at the output of MAPPING module

Testing DUC/DDC Implementation Designing prope filte fo DUC/DDC Filter Filter 1 Stop band attenuation277 dBs

Filter of 245 taps. Introduced Delay (DUC-DDC) filters (two filters D=2) assuming an interpolation by N=4 is: Delay=(((245-1)/2)/N)·D = 61 Ts Transition band from 5400Hz to 7700Hz

It is a multiple of Ts

Testing DUC/DDC Implementation Designing prope filte fo DUC/DDC Filter Received RAMP at the output of DEMAPPING

Still with DMRS signals For reference purposes only Transition band from 5400Hz to 7700Hz

Testing DUC/DDC Implementation Now only the clean RAMP received.

Notice the perfect recovery of the RAMP signal.

Testing DUC/DDC Implementation Designing prope filte fo DUC/DDC Filter Filter 2 Stop band attenuation277 dBs

Filter of 243 taps. Introduced Delay (DUC-DDC) filters (two filters D=2) assuming an interpolation by N=4: Delay=(((243-1)/2)/N)·D = 60.75 Ts Transition band from 5400Hz to 7700Hz

It is not multiple of Ts

Testing DUC/DDC Implementation Designing prope filte fo DUC/DDC Filter Received RAMP at the output of DEMAPPING

NOTICE THE STRONG DISTORTION

Transition band from 5400Hz to 7700Hz

DUC/DDC DECIMATION ecimatio : Time considerations

 What happen when synchronisation is lost?

 We choose one (orange for example) that differs from the optimal one

Distortion would appear

Samples not time aligned

Testing DUC/DDC Implementation Designing prope filte fo DUC/DDC Filter Filter 3 ONLY 91dBs Attenuation at stop band 91 dBs only

Filter of 105 taps. Introduced Delay (DUC-DDC) filters (two filters D=2) assuming an interpolation by N=4: Delay=(((105-1)/2)/N)·D = 26 Ts Transition band from 5400Hz to 7700Hz

It is multiple of Ts

Testing DUC/DDC Implementation Designing prope filte fo DUC/DDC Filter

NOTICE ...SMALL DISTORTION

Transition band from 5400Hz to 7700Hz

Testing DUC/DDC Implementation Designing prope filte fo DUC/DDC Filter Filter 4 ONLY 91dBs

Moving transition band to left

Attenuation at stop band 91 dBs only Transition band reduced to 4400Hz to 6700Hz

Filter of 105 taps. Introduced Delay (DUC-DDC) filters (two filters D=2) assuming an interpolation by N=4: Delay=(((105-1)/2)/N)·D = 26 Ts It is multiple of Ts

Testing DUC/DDC Implementation Designing prope filte fo DUC/DDC Filter

NOTICE ... STRONGER DISTORTION

Transition band from 4400Hz to 6700Hz

Testing DUC/DDC Implementation Filte Requirement fo DUC/DDC Uplink (FFT 128) N=4 With PUCCH

3375Hz

8625Hz

24000Hz

2250Hz

9750Hz

24000Hz

Withou PUCCH

Testing DUC/DDC Implementation Filte Requirement fo DUC/DDC Uplink (FFT 256) N=4 With PUCCH

4219Hz

7781Hz

24000Hz

3656Hz

8343Hz

24000Hz

Withou PUCCH

Testing DUC/DDC Implementation Ideal Signal

IF Filter

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fo

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Multiply by 𝑒 −𝑗ωot

DDC Process

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Interpolate by 2

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Filter to remove this component

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Testing DUC/DDC Implementation IF Filter

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fs/2

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Multiply by 𝑒 −𝑗ωot

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Interpolate by 2

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Filter to remove this component Undesired signal still present 0

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Testing DUC/DDC Implementation IF Filter

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Multiply by 𝑒 −𝑗ωot

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Interpolate by 2

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Filter to remove this component Undesired signal strongly reduced 0

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