Lab 6 REPORT WITH MULTISIM CIRCUIT PDF

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ENS 221 Lab reports complete with Multisim circuit...

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The College of Staten Island

ENS 221 Spring 2021 LAB 6: Design with Multiplexers Instructor: Erlan H. Feria Group #3 Hamzah Farah Partner: Antonio Hernandez Date Handout Submitted: 3/10/2021 Date Report Submitted: 3/20/2021

I.

Introduction:

In this week experiment, we will learn how to use and design different types of multiplexers. A multiplexer is a combinational circuit which have many data inputs and single output depending on control or select inputs. we can say that for 2n input lines, n selection lines are required. Multiplexers are mainly used to increase amount of the data that can be sent over the network within certain amount of time and bandwidth. This laboratory consists of four tasks, the first task represents a simple multiplexer and demultiplexer circuit designs as introduction of the of their functionality, this task focuses on deriving the truth tables and building the circuits 2-to-1 MUX and a 1-to-2 demultiplexer using AND, inverter, and OR gates. The second task is asking us to build an ALU combinational circuit that performs basic arithmetic and logic operations: ADD, AND, OR and NOT. This circuit is built using the multiplexer IC 74153 gate, 7404 NOT gate, 7408 AND gate, 7432 OR gate, and 7486 XOR gate and then tested on Multisim. The third task focuses on building a 4-bit parity generator using a 74151 multiplexer IC gate. We are asked to derive the truth table and verify it by constructing the circuit design on the Multisim software. In addition to using 74151 IC chip, an inverter 7404 IC gate will be used to build the circuit. The final task of this experiment is asking us to build a full adder circuit with 2 4x1 multiplexers or (1 8X1 multiplexer) 74153 IC chip. In order to build this circuit, we require other than the multiplexers chip an additional NOT 7404 gate.

II.

Methods:

A. Materials: •

Two 7404 NOT gates

•

74151 8-to-1 MUX

•

74153 Dual 4-to-1 MUX

•

7432 OR gate

•

7486 XOR gate

•

Two 7408 AND gates

•

Multisim Software

B. Experimental procedure: Task1: Task 1 is divided into two parts. In the first part we build a 2-to-1 MUX, using two AND gate , an inverter , and one OR gate to construct the circuit. For part 2 we build a 1-to-2 demultiplexer using two inverter gates, and two AND gates. First, we derive the truth tables for both the circuits and then we build the circuits on the Multisim software following the circuit diagrams given in the handout.

The truth table for the 2*1 Multiplier X

Y

S

M

0

0

0

0

0

0

1

0

0

1

0

0

0

1

1

1

1

0

0

1

1

0

1

0

1

1

0

1

1

1

1

1

Truth Table for the 1*2 demultiplexer A

In

OUT0

OUT1

0

0

0

0

0

1

1

0

1

0

0

0

1

1

0

1

Task2: For Task 2, we are we are building an ALU Combinational Circuit that performs basic arithmetic and logic operations: ADD, AND, OR and NOT. To build this, we need multiplexer IC 74153, Inverter gate, AND gate, OR gate, and XOR gate as shown in the given diagram. The truth table is given, we only need to construct the circuit on Mutisim and verify that truth table using SPDT switches.

Task3: For Task 3, we will be building a 4-bit even parity generator using a multiplexer chip. To do this, we need 74151 multiplexer IC chip, and one 7404 NOT gate. First, we drive the truth table for the circuit in order to make the right connections and picking the correct in pins for the multiplexer chip, then test circuit design on Multisim software using SPDT switches and probes

Truth Table for the 4 bit – parity generator circuit: INPUTS X1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

X2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

X3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

X4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

OUTPUT P 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0

P=X4 P=X4’ P=X4’ P=X4 P=X4’ P=X4 P=X4 P=X4’

Task4: Task 4 is similar to task 3 in the steps taken to design the circuit, but we will be building a Full Adder Circuit instead of a parity bit as in the previous task. This full adder circuit is built using 8x1 multiplexers 74153 IC chip, and one 7404 NOT gate. As done in the previous task, we derive the truth table for circuit then verify results using logic converter on Multisim in order to match the derived truth table.

Truth Table for the Full Adder Circuit. INPUTS

OUTPUT

A

B

Cin

S

Cout

0 0

0 0

0 1

0 1

0 0

S=Cin Cout=0

0 0

1 1

0 1

1 0

0 1

S=Cin’ Cout=Cin

1 1

0 0

0 1

1 0

0 1

S=Cin’ Cout=Cin

1 1

1 1

0 1

0 1

1 1

S=Cin Cout=1

III. Results:

Task1: (a) 2-to-1 MUX Multisim Simulation for the 2*1 Multiplexer using Switches and Probes

Multisim Simulation for the 2*1 Multiplexer using logic converter

(b) 1-to-2 demultiplexer Multisim Simulation: for the 1*2 Demultiplexer using Switches and Probes

Task2:

Multisim Simulation for ALU Combinations circuit using switches and prob

Task3:

Multisim Simulation for the 4-bit even parity generator Circuit using Switches and Probe

Task4: Multisim Simulation for the 4-bit Parity Generator Circuit using Switches and Probes

Full Adder Circuit using Logic Converter: •

Sum

•

Cout

IV. Discussion: In this week laboratory experiment I have learned to build and use the multiplexer in combinational circuit design. I learned that multiplexers are circuits that are usually used to minimize the selection for the output lines from many input lines to one or two lines. For the first task of the experiment, I learned how to build the simplest design of a multiplexer and demultiplexer circuit and verify my results using a logic converter. To build the 2-1 multiplexer, we needed to use a combination of AND, NOT, and OR gates. This circuit converts 4 selected input lines to only one output line. the demultiplexer circuit behaves as the opposite of a normal 2-1 multiplexer, as this circuit converts 1 selected input line to 2 output lines, we needed 2 inverters and 2 AND gates to design this circuit and verified its result using SPDT switches and probes. For the second, I learned another type of multiplexer which is specifically the ALU combinational circuit. In order to build an ALU circuit, I used a 4x1 MUX chip, XOR, AND, OR, and NOT gates. I did some review in chapter 4 in the textbook of how the design of the circuit should look like, and reviewed the function of the input switches S1, and S2 and how it determines the operation that will be performed in the circuit. I followed the design given in the handout and confirmed the operation result using SPDT switches for the input and probe for the output. Then I learned in the third task of this experiment how to build a circuit using an 8-1 multiplexer combinational circuit. We were asked to design 4-bit even parity generator circuit using a multiplexer chip, the even parity generator circuit outputted 0 when the number of 1’s were even and outputted 1 when the number of 1’s were odd. I designed the circuit according to the derived truth table on Multisim software using a 74151-multiplexer chip, and a 7404 NOT gate. This circuit

has 4 inputs X1, X2, X3, and X4, where X4 is the selected input line for the multiplexer and produces the output P, the output P ended up either same as X4 or the invert of it. Finally, for the last task of the experiment I learned how to Implement a full adder with 2 4x1 multiplexers combinational circuit. I used an 8x1 74153 multiplexer chip instead of 2 4x1 as what it says in the handout. to build this full adder I needed to use one 7404 NOT gate beside the multiplexer 74153 chip. This circuit had 3 inputs A, B and Cin (3 switches) that produced two outputs Sum and Cout. I derived the truth table first to make the correct connection for the multiplexer chip input pins. I used SPDT switches, VCC and ground as inputs, and used probes to represent the outputs, then verified my truth table using logic converter for each output Sum and Cout.

V.

Conclusion:

In my conclusion, in this laboratory I learned a new type of combinational circuit which is the multiplexer circuit, and the function of the multiplexer where it selects input lines from the multiple inputs and converts them to a single output. I also learned how to design the simplest format of a Multiplexer and demultiplexer circuits. Furthermore, this lab taught me how to use the multiplexer to choose between arithmetic operations within one circuit , also how to use the Multiplexer chip to build a parity bit generator and a full adder circuit. I feel that the content of this lab was very beneficial to add to my knowledge on how to build these circuits using different components that what I have learned in the previous laboratory experiments. Overall, all calculations and computations equated perfectly, when testing all the circuits designs on Multisim had showed the exact same results as their derived truth tables. Therefore, this lab was a success.

References: • • •

Lecture notes Digital design textbook 5th ed https://www.geeksforgeeks.org/multiplexers-in-digital-logic/...