LAB2 En - 2nd lab Circuit simulation and Circuit Analysis PDF

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2nd lab Circuit simulation and Circuit Analysis...

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Universität Duisburg-Essen

PRACTICAL TRAINING TO THE LECTURE

FCE 1 Experiment 2 Circuit simulation and Circuit Analysis

Name:

Matriculation-Number:

First Name:

Group-Number:

Tutor:

Date:

All questions marked with Q1 to Qn must be answered before the lab begins. All tasks marked with T1 till Tn must be completed to finish the lab.

Prof. Dr.Ing. Axel Hunger Dipl.Ing. Joachim Zumbrägel Universität Duisburg-Essen Faculty of Engineering, Department Electrical Engineering and Information Technology Computer Engineering

Copyright (C) Computer Engineering

FCE1 Lab

Experiment 2: Circuit simulation and Circuit Analysis

Introduction The first experiment is supposed to teach you how to design and simulate simple logical circuits on your own. Therefore, in the first part of the experiment you will be given the logical circuit that is to be simulated. In the second part you will be asked to design a Gray Code converter. The next chapter deals with adders, presenting a technical problem for you to solve using logical circuits. The last chapter gives you an introduction to hierarchical blocks and their use in logical design. Note: You are expected to have read and understood the introductory lab materials. Please, bring this document with you on your lab date.

1. Creating a sample logical circuit OrCAD gives its users the opportunity to create their circuits using either ideal or real parts.

Fig. 1.1: Sample circuit Before we begin this lab, however, you should be able to answer the following questions concerning the sample logical circuit in Fig. 1.1 and some basic knowledge about OrCAD: Q1: Which application from the OrCAD suite do we use to create and edit logical circuits? Which application is responsible for their simulation?

Q2: Explain what the term propagation delay means.

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

Q3: What is the difference between real and ideal parts?

Q4: How would OrCAD interpret two wires having the same Net Alias?

Q5: What should you apply in order to observe the behavior of a signal during simulation?

Q6: What does “Run to time” represent?

Q7: In order to generate input signals for a circuit, OrCAD uses different kinds of sources. Name two sources you know and point out the differences between them.

Q8: The impulse diagram in Fig. 2.1 represents the behavior of the input signals A1 and B1 during a simulation. Write down the COMMAND patterns necessary to achieve this behavior.

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

Q9: Write the truth table corresponding to the sample logical circuit on Fig. 1.1 and derive the logical expressions for its outputs.

OUT1:

OUT2:

Now that you have answered all the questions you can proceed to the next task. T1: Build two variants of the sample circuit shown in Fig. 1.1: one with ideal parts named TESTA[Gr.Nr.] and another with real parts named TESTB[Gr.Nr.]. Note: Ideal parts that can be simulated with PSPICE are in the DIG_PRIM.OLB library.

2. Simulating the sample logical circuits T2: After you have completed your designs, create and run simulations for each one. For more information on simulating logical circuits, read your introductory document. Remark: If you name two or more wires with the same alias, OrCAD will interpret them as one continuous wire. In order to get correct results out of your simulations, be sure to set unique aliases for each individual wire you place. T3: Use the signal patterns illustrated in Fig. 2.1 and Fig. 2.2 as input and fill in the output for the two logical circuits.

Fig. 2.1: Impulse diagram for ideal parts

Fig. 2.2: Impulse diagram for real parts

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

3. Developing a Code Converter In the digital world it is often the case that data has to be coded and converted from one code to another. For the coding process a number of different codes are used. What we will attempt to develop in this exercise is a real world code converter, which unlike our previous sample logical circuit, does meaningful calculations. In order to resemble a real, working circuit, we have to use real parts to build it. As we saw in our former simulations, real parts imply time propagation delay. The purpose of our logical circuit is to take the decimal numbers from 0 to 7 represented as 3-bit binary code and convert them into a 3-bit Gray-Code, as shown in Table 3.1. The development process consists of three steps: 1. Determine the logical expressions, which perform the conversion. 2. Design a circuit that implements those expressions. 3. Simulating the designed circuit. Use Table 3.1 to deduce the expressions, which convert Binary-Code bits into Gray-Code bits.

Binary-Code

Gray-Code

Decimal Number

A

B

C

D

E

F

0

0

0

0

0

0

0

1

0

0

1

0

0

1

2

0

1

0

0

1

1

3

0

1

1

0

1

0

4

1

0

0

1

1

0

5

1

0

1

1

1

1

6

1

1

0

1

0

1

7

1

1

1

1

0

0

Table 3.1: Binary-Code and Gray-Code We have given you the expression for bit D below. The rest you have to find on your own. D in disjunctive normal form (DNF) D = (A ⋅ B ⋅ C )+ (A ⋅ B ⋅ C )+ (A ⋅ B ⋅ C )+ (A ⋅ B ⋅ C ) D in conjunctive normal form (CNF) D = ( A + B + C )⋅ (A + B + C )⋅ (A + B + C )⋅ (A + B + C )

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

Q10: Write down the disjunctive and conjunctive normal forms of bits E and F. DNF: E=________________________________________________________________ F=________________________________________________________________ CNF: E=________________________________________________________________ F=________________________________________________________________

Q 11: Simplify the logical expressions for all Gray-Code bits (D, E and F) using Boolean arithmetic and KV-maps.

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

The circuit of the code converter in Fig. 3.1 is built using the simplified expressions for the bits D, E and F. Compare its design to your results.

Figure 3.1: Code Converter T4: Create the code converter circuit in OrCAD and simulate it using the input values in Fig. 3.2 for A, B and C. Complete the impulse diagram for D, E and F. Save your cicuit as CONVERTER[Gr.Nr.]

Figure 3.2: Impulse Diagram

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

4. Adders Arithmetic is probably the most basic thing you can do with a computer and addition is the most frequently performed arithmetic operation in digital systems. In this particular exercise we will attempt to develop the simplest arithmetic circuit, the adder.

4.1 Half Adder The simplest adder is the half adder (HA). It adds two input bits A and B producing a 2-bit sum, which is represented by S and a carry bit C as shown in the logic circuit symbol in Fig. 4.1.1. The carry - C indicates if the sum was greater than 1 or not. The operation formula and the truth table for the half adder are shown in 4.1.3 and 4.1.4 respectively.

Input bit A

A

HA Input bit B

B

S

Sum

C

Carry

Fig. 4.1.1

A

Augend

+B

Addend

CS Sum Carry Fig. 4.1.3

Fig. 4.1.2

A

B

C

S

0

0

0

0

0

1

0

1

1

0

0

1

1

1

1

0 Fig. 4.1.4

We can easily obtain the Boolean functions from the truth table for the two outputs – the sum S and the carry C.

(

)

S = (A ⋅ B )+ B ⋅ A ⇒ S = ( A ⊕ B ) C = A⋅ B

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

4.2 Full Adder The half adder has severe limitations because it cannot take in a carry from any previous addition of two bits. A full adder (FA), however, overcomes these drawbacks by being able to add 3 bits. The FA features three input bits, A, B and carry-in Cin, and two output bits Cout and S. The truth table and the logic circuit symbol of the FA are shown in Fig. 4.2.1.

Input bit A

A

Carry-in

A

B

Cin

Cout

S

Cin

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

FA Input bit B

B

S

Sum

Cout

Carry-out

Fig. 4.2.1: Logical circuit symbol and truth table

Q12: Derive the Boolean functions for the sum S and the carry Cout , as function of the inputs A, B and Cin , in minimized form.

Cout = _______________________________________________________________

S = ________________________________________________________________

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

T5: Derive the functions for S and Cout from the circuit in Fig. 4.2.2 and compare them to your minimized equivalents from Q12. Does the circuit in Fig. 4.2.2 fulfill the specifications of a FA?

Fig. 4.2.2

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

T6: Simulate the circuit in Fig. 4.2.2 using the inputs from the impulse diagram shown in Fig. 4.2.3. Sketch the resulting outputs of the simulation. The circuit should be named FA[Gr.Nr.].

Fig. 4.2.3

5. Circuit Analysis In this part of the practical training you have to analyze a hierarchical block. You will be given a hierarchical block named FBLKBOX that represents an unknown sub-circuit. Your task is to determine the logical behavior of the block with a suitable input signal. Determine the truth table and deduce the according Boolean expressions for all inputs and outputs. Open the project named Lab1, navigate to the schematic named FBLKBOX and open the FBLKBOX schematic page (Fig. 6.1). Place and connect a signal source to each input and define an appropriate signal pattern in order to observe the behavior of the hierarchical block.

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

T7: Create and run a simulation and analyze the results for the output F. Set up the truth table for the FBLKBOX and derive the function for F.

A

B

C

F

Fig. 6.1: FBLKBOX

F=

T8: Sketch a logical circuit matching the behavior of the FBLKBOX you analyzed.

Ask the tutor to find out how to open the circuit corresponding to the black box. Now look at the schematic that is represented by the FBLKBOX and compare it to your design.

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FCE1 Lab

Experiment 1: Circuit simulation and Circuit Analysis

Digital Components

Symbol-Name

Type-Number

Library

NOT

7404

7400

7408

7400

7411

7400

7400

7400

7410

7400

7420

7400

7432

7400

7402

7400

7427

7400

7486

7400

7473

7400

AND 2-Input AND 3-Input NAND 2-Input NAND 3-Input NAND 4-Input OR 2-Input NOR 2-Input NOR 3-Input XOR JK-FF with CLR JK-FF with PRE/CLR JK-FF with CLR JK-FF with PRE/CLR D-FF with PRE/CLR

7476

7400

74107

7400

74109

7400

7474

7400

D-FF

7474

7400

74LS173A

74ls

74170

7400

74LS197

74ls

BINARY COUNTER

7493A 74293 74177

7400

ROM 32⋅8 5 Input, 8 Output 32 bytes memory

ROM 32⋅8

BREAKOUT

D-TYPE REGISTER REGISTER FILE O.C. PRESETTABLE BINARY COUNTER

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