Lec 12c-Decoders - Lecture notes 12c PDF

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14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #10: Decoders

General Decoder Structure  A decoder is a logic circuit that converts coded inputs into coded outputs.  Each input code word produces a different output code word (there is a one-to-one mapping between inputs and outputs) Decoder input code word

ma p

output code word

enable inputs 2 of 20

1

Decoder Example  BCD to seven-segment decoder – has 4-bit BCD as input code and the “seven-segment code” as its output code

g

f Vcc a

b

decoder

BCD code

a

a b c d e f g

f

b

g

e

c d

() BCD = binary-coded decimal

e

d Gnd c dp

3 of 20

Binary Decoder  Accepts a n-bit binary input code and generates a 1-out  

of-2n output code Used to activate exactly one of 2n outputs based on n-bit input value Examples: 2-to-4, 3-to-8, 4-to-16, etc. Note: BCD to seven-segment decoder is NOT a binary decoder – Because multiple outputs active simultaneously

 Binary decoders are

n-bit input

simple and general; binary combination (“code”) can be used to build general decoders (shown later) enable inputs

Decoder ma p

#1 index number of an output line #2n 4 of 20

2

Gate Level Implementation of Decoders active-high enable:

■ 1:2 decoders

G

active-low enable: G_L

O0

O0

S

S O1

O1 active-low enable:

active-high enable: G

G_L

O0

■ 2:4 decoders S1

O0

O1

O1

O2

O2

O3

O3

S0

S1

S0 5 of 20

How It Works ■ 2:4 decoder: – input combination: “00” – output: O0

G

O0

– input combination: “10” – output: O2

G

O0

O1

O1

O2

O2

O3

O3

S1

S0

S1

S0

0

0

1

0 6 of 20

3

Binary 2-to-4 Decoder 2-to-4 decoder

Inputs

Outputs

I0

Y0

EN

I1

Y1 Y2 Y3

0

x

x

0

0

0

0

1

0

0

0

0

0

1

EN

I1

I0

Y3 Y2 Y1 Y0

1

0

1

0

0

1

0

1 1

1 1

0 1

0 1

1 0

0 0

0 0

Note “x” (don’t care) notation.

 Note that the outputs of the decoder correspond to the minterms: Yi = mi – –

e.g., Y0 = I1 · I0 Y1 = I1 · I0

etc. 7 of 20

MSI 2-to-4 Decoder (* COMPARE TO Wakerly, 4th edition, Figure 6-32(b), page 385 )

(4)

EN

(5)

(6)

I0

Y0_L

(1)

Y1_L

Y2_L

(2) (7)

I1

(3)

Y3_L

■ Input buffering (less load on input circuit) ■ NAND gates (faster operation) 8 of 20

4

Complete 74x139 Decoder (4)

1Y0_L

(1)

1G_L

74x139

(5)

1

1Y1_L (6)

3

1Y2_L

(2)

1Y0

4

1Y1

5

1A

1Y2

6

1B

1Y3

7

2Y0

12

2Y1

11

2A

2Y2

10

2B

2Y3

9

1G 2

1A (7)

(3)

1B

1Y3_L

15

2G 14 13

(12)

2Y0_L

(15)

2G_L

(11)

2Y1_L

(10)

2A 2B

2Y2_L

(14)

Two 2-to-4 decoders in a single packaging

(9)

(13)

2Y3_L

(* COMPARE TO 74x138 3-to-8 decoder, described next ) 9 of 20

74x138: 3-to-8 decoder  Commercially available MSI 3-to-8 decoder – Note that its outputs are active low » because TTL and CMOS inverting gates are faster than non-inverting gates 74x138 6

■ Logic equations for internal output signals include “enable” signals. ■ Example: Y5 = G1 · G2A · G2B · C · B · A

Y0

15

5

G2A

Y1

14

4

G2B

Y2

13

Y3

12

Y4

11

Y5

10

Y6

9

Y7

7

1

A

2

B

3

enable

select

outputs

G1

C

10 of 20

5

Truth Table for a 3-to-8 Decoder Inputs

Outputs C

G1 G2A_L G2B_L

B

A

Y7_L Y6_L Y5_L Y4_L Y3_L Y2_L Y1_L Y0_L

0

x

x

x

x

x

1

1

1

1

1

1

1

1

x

1

x

x

x

x

1

1

1

1

1

1

1

1

x

x

1

x

x

x

1

1

1

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

1

1

1

0

1

0

0

0

0

1

1

1

1

1

1

1

0

1

1

0

0

0

1

0

1

1

1

1

1

0

1

1

1

0

0

0

1

1

1

1

1

1

0

1

1

1

1

0

0

1

0

0

1

1

1

0

1

1

1

1

1

0

0

1

0

1

1

1

0

1

1

1

1

1

1

0

0

1

1

0

1

0

1

1

1

1

1

1

1

0

0

1

1

1

0

1

1

1

1

1

1

1

■ Because of the inversion bubbles, we have the following relations between internal and external signals G2A = G2A_L Y5 = Y5_L etc.

11 of 20

3-to-8 Decoder Logic Diagram (NOR gate)

G1

(6)

(15)

Y0_L

(14)

Y1_L

(13)

Y2_L

(4)

G2A_L G2B_L

A

(5)

(12)

(11)

Y4_L

(10)

Y5_L

(1)

(2)

(9)

(3)

(7)

B C

Y3_L

Y6_L

Y7_L

12 of 20

6

Decoder Cascading ■ Decoders can be cascaded hierarchically to decode larger code words 74x138

+5V R 6 5 4

■ Example: Design a 4-to-16 decoder using 74x128s (3-to-8 decoders)

G1

Y0

15

DEC0_L

G2A

Y1

14

DEC1_L

Y2

13

DEC2_L

Y3

12

DEC3_L

Y4

11

DEC4_L

Y5

10

DEC5_L

Y6

9

DEC6_L

Y7

7

DEC7_L

G2B

1

A 2 B

N0 N1

3

N2 N3

C

U1

EN_L

74x138 6

G1

Y0

15

DEC8_L

G2A

Y1

14

DEC9_L

Y2

13

DEC10_L

Y3

12

DEC11_L

Y4

11

DEC12_L

A

Y5

10

DEC13_L

B 3 C

Y6

9

DEC14_L

Y7

7

DEC15_L

5 4

G2B

1 2

U2

13 of 20

More Cascading 74x138 6

5-to-32 decoder

G1

5

G2A

4

G2B N0

1 2

N1

3

N2

A B C

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

15 14 13 12 11 10 9 7

DEC0_L DEC1_L DEC2_L DEC3_L DEC4_L DEC5_L DEC6_L DEC7_L

U2 74x138 6

G1

5

G2A G2B

4

1

74x139 EN3_L N3 N4

1

1G 2 3

1A 1B

2

Y0 Y1 Y2 Y3 U1

4 5 6 7

EN0X7_L EN8X15_L EN16X23_L EN24X31_L

3

A B C

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

15 14 13 12 11 10 9 7

DEC8_L DEC9_L DEC10_L DEC11_L DEC12_L DEC13_L DEC14_L DEC15_L

U3 74x138 6

G1 G2A

5 4

G2B 1 2

EN1 EN2_L

3

A B C

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

15 14 13 12 11 10 9 7

DEC16_L DEC17_L DEC18_L DEC19_L DEC20_L DEC21_L DEC22_L DEC23_L

U4 74x138 6

G1

5

G2A

4

G2B 1 2 3

A B C

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

15 14 13 12 11 10 9 7

DEC24_L DEC25_L DEC26_L DEC27_L DEC28_L DEC29_L DEC30_L DEC31_L

U5

14 of 20

7

Decoder Applications  Microprocessor memory systems – Selecting different banks of memory

 Microprocessor input/output systems – Selecting different devices

 Microprocessor instruction decoding – Enabling different functional units

 Memory chips – Enabling different rows of memory depending on address

 Lots of other applications 15 of 20

Decoders as General-Purpose Logic  n-to-2n decoders can implement any function of n variables

– with the variables used as control inputs – the appropriate minterms summed to form the function 3-to-8 decoder A B C

I0 I1 I2 EN

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

A·B·C A·B·C A·B·C A·B·C A·B·C A·B·C A·B·C A·B·C

decoder generates appropriate minterm based on control signals (it “decodes” control signals)

16 of 20

8

Decoders as General-Purpose Logic ■ F1 = A·B·C·D + A·B·C·D + A·B·C·D ■ F2 = A·B·C·D + A·B·C

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15

4-to-16 decoder

■ F3 = A + B + C + D

A

I0

B C D

I1 I2 I3

EN

A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D A·B·C·D

F1

F2

F3 17 of 20

Customized Decoder Circuit CS_L

RD_L

A2

A1

A0

Output(s) to Assert

1

x

x

x

x

none

x 0

1 0

x 0

x 0

x 0

none BILL_L, MARY_L

0

0

0

0

1

MARY_L, KATE_L

0

0

0

1

0

JOAN_L

0 0

0 0

0 1

1 0

1 0

PAUL_L ANNA_L

0

0

1

0

1

FRED_L

0

0

1

1

0

DAVE_L

0

0

1

1

1

KATE_L

Truth table

74x138

+5V

CS_L RD_L

Circuit diagram

A0 A1 A2

BILL_L 74x08

R

G1

Y0

15

1

5

G2A

Y1

14

2

4

G2B

Y2

13

Y3

12

PAUL_L

Y4

11

ANNA_L

Y5

10

Y6

9

Y7

7

6

1

A 2 B 3

C

3

MARY_L U2 JOAN_L

FRED_L DAVE_L 74x08 4

U1

6

KATE_L

5

U2

18 of 20

9

Decoder-Based Circuits (a) X·Z

Designing a circuit for the logic function F = ∑X,Y,Z (0,2,3,5): (a) Karnaugh map; (b) NAND-based minimal sum-of-products; (c) decoder-based canonical sum.

X

XY

00 01 11 10

Z

0

0

1

1

1

2

1

6

4

3

1

7

5

X·Y

Z

1

X·Y·Z

Y

74x04 1

2

Z

Z

74x00 1

U1

3

4

X

U1

4 5

6

6

U1

3 4 5

6

5

F

4

(X·Y)

Z

74x00

Y X

(X·Y·Z)

12

2 13

U3

(b)

G1

Y0

15

Y1

14

1

G2A

13

2

G2B

Y2 Y3

12

4

Y4

11

5

U3

Y 1

6

74x10

U2

74x04

74x138

+5V R

74x00

Y 5

(X·Z)

U2

74x00 X

3

2

1

A

Y5

10

2

B C

Y6

9

Y7

7

3

(c)

74x20 6

F U2

U1

19 of 20

Multiple Decoding w/ a Single Decoder

74x08 74x138

+5V R

Z Y X

6

G1

Y0

15

5

G2A

Y1

14

4

G2B

Y2

13

Y3

12

Y4

11

1

A

10

2

Y5

B C

Y6

9

Y7

7

3

U1

1 2 13

12

H = ∑X,Y,Z (2,4,5)

U2 74x08 3 4 5

6

G = ∑X,Y,Z (0,1,3)

U2 74x08 11 10 9

8

F = ∑X,Y,Z (3,6,7)

U2

20 of 20

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