Modern Digital Electronics Solutions RP JAIN PDF

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Modern Digital Electronics Solutions RP JAIN...

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Solution Manual for Modern Digital Electronics Third Edition

R P Jain

CHAPTER 1 1.1 (a) Analog. The output of a pressure gauge is proportional to the pressure being measured and can assume any value in the given range. (b) Digital. An electric pulse is produced for every person entering the exhibition using a photoelectric device. These pulses are counted using a digital circuit. (c) Analog. The reading of the thermometer is proportional to the temperature being measured and can assume any value in the given range. (d) Digital. Inputs are given with the help of switches, which are converted into digital signals 1 and 0 corresponding to the switch in the ON or OFF position. These signals are processed using digital circuits and the results are displayed using digital display devices. (e) Analog. It receives modulated signals which are analog in nature. These signals are processed by analog circuits and the output is again in the analog form. (f) Digital. It has only two possible positions (states), ON and OFF. (g) Digital. An electric pulse is produced for every vote cast by pressing of switch of a candidate. The pulses thus produced for each candidate are counted separately and also the total number of votes polled are counted. 1.2 (a) (i)

(iii)

S1

S2

Bulb

OFF OFF ON ON

OFF ON OFF ON

OFF OFF OFF ON

S

Bulb

OFF ON

ON OFF

S1

S2

Bulb

0 0 1 1

0 1 0 1

0 0 0 1

S

Bulb

0 1

1 0

(ii)

(iv)

S1

S2

Bulb

OFF OFF ON ON

OFF ON OFF ON

OFF ON ON ON

S1

S2

Bulb

OFF OFF ON ON

OFF ON OFF ON

OFF ON ON OFF

S1

S2

Bulb

0 0 1 1

0 1 0 1

0 1 1 1

S1

S2

Bulb

0 0 1 1

0 1 0 1

0 1 1 0

(b) (i)

(iii)

(c)

(i) AND

(ii) OR

(ii)

(iv)

(iii) NOT

(iv) EX-OR

1.3 1 Input A 0

0

1

2

3

4

5

t(ms)

0

1

2

3

4

5

t(ms)

1 Input B 0

1 AND 0

1 OR 0

1 NAND 0

1 NOR 0

1 EX-OR 0

1.4 A

Inputs B

(a)

Outputs of (b) (c)

(d)

0 0 1 1

0 1 0 1

1 0 0 0

1 1 1 0

0 1 1 1

The operations performed are (a) NOR (b) NAND

(c) AND 2

(d) OR

0 0 0 1

1.5

For Fig. 1.6 (a)

(c)

(b)

A

B

AB

Y

0 0 1 1

0 1 0 1

1 1 1 0

0 0 0 1

A

Y

0 1

1 0

A

B

A

B

Y

0 0 1 1

0 1 0 1

1 1 0 0

1 0 1 0

0 1 1 1

A

Y

(b)

0 1

1 0

A

B

0 0 1 1

0 1 0 1

For Fig. 1.8 (a)

(c)

1.6

(a) NAND, NOR (c) NAND

1.7

(a)

A 1 1 0 0

A

B

0 0 1 1

0 1 0 1

B

Y

1 0 1 0

0 0 0 1

A

Y

B

1 0 0 0

0 1 1 1

(b) AND (d) OR

Inputs A

B

0 0 1 1

0 1 0 1

AB

AB

0 0 1 0

0 1 0 0

Output Y 0 1 1 0

(b) EX–OR (c) A

Y

B 3

(d) \

Y = AB

AB

AB

AB

Y

AB A B

Y =Y

AB AB Y1 Y2

where,

Y1

AB

and

Y2

AB

A Y1 Y

B

1.8

1.9

Y2

For simplicity, we shall consider 2-input gates, but the results are equally valid for any number of inputs. In the positive logic system, the higher of the two voltages is designated as 1 and the lower voltage as 0. On the other hand in the negative logic system, the lower of the two voltage is designated as 1 and the higher voltage as 0. Therefore, if 1s and 0s are interchanged, the logic system will change from positive to negative and vice-versa. (a) In the truth table of positive logic AND gate replace all zeros by ones and all ones by zeros. The resulting truth table is same as that of the OR gate. Similarly, if all ones and zeros are interchanged in the truth table of the OR gate, the resulting truth table will be same as that of the AND gate. (b) Repeat part (a) for NAND and NOR gates. (a) A + A B + A B = (A + A B ) + A B = A (1 + B ) + A B = A × 1 + AB = A + AB = (A + A ) (A + B) = A + B (b) AB + A B + A B = (A + A ) B + A B = B + A B = (B + A ) (B + B ) = A +B (c) A BC + A B C + AB C + ABC = A BC + A B C + AB (C + C ) = A BC + A B C + AB = A BC + A (B + B C) = A BC + A (B + B ) (B + C) 4

= A BC + AB + AC = C (A + A B) + AB = C (A + A ) (A + B) + AB = C (A + B) + AB = AB + BC + CA 1.10 (a) A

B

AB

AB

A + A B + AB

A+B

0 0 1 1

0 1 0 1

0 1 0 0

0 0 1 0

0 1 1 1

0 1 1 1

(b) A

B

AB

AB

AB

AB + A B + A B

A +B

0 0 1 1

0 1 0 1

0 0 0 1

0 1 0 0

1 0 0 0

1 1 0 1

1 1 0 1

(c)

1.11

A

B

C

A BC

AB C

AB C

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 1 0 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 0 1 0

ABC LHS 0 0 0 0 0 0 0 1

0 0 0 1 0 1 1 1

AB

BC

CA

RHS

0 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 1

0 0 0 1 0 1 1 1

(a) The realization of LHS requires, two inverters, two 2-input AND gates, and one 3-input OR gate, whereas the realization of RHS requires only one two input OR gate.

A A B B

(i)

(ii) 5

(b) The realization of LHS requires two inverters, three 2-input AND gates and one 3-input OR gate, whereas the realization of RHS requires only one inverter and one 2-input OR gate. A A B

B

(ii)

(i)

(c) The realization of LHS requires three inverters, four 3-input AND gates and one 4-input OR gate, whereas the realization of RHS requires only three 2-input AND gates and one 3-input OR gate.

A

B C

(i) A B

C

(ii)

1.12

(a) AB + CD

AB CD

AB CD

6

(b) (A + B) (C + D)

(A

B ) (C

D)

( A B) ( C D) (i) The left hand side of (a) can be realized by using two 2-input AND gates followed by one 2-input OR gate, while the right hand side is realizable by two 2-input NAND gates followed by another 2-input NAND gate. Hence an AND-OR configuration is equivalent to a NANDNAND configuration. (ii) The left hand side of (b) is realizable by two 2-input OR gates followed by a 2-input AND gate, while the right hand side is realizable by two 2-input NOR gates followed by another 2-input NOR gate. Hence an OR-AND configuration is equivalent to a NOR-NOR configuration. 1.13 (a)

A

A

B

B Y

Y C

C

D

D (i)

(b)

(ii)

A

A

B

B Y

C

C

D

D

Y

(i)

(ii)

1.14 (a) Since A × B = B × A Therefore, the AND operation is commutative. If A × (B × C) = (A × B) × C, then the AND operation is associative. This can be proved by making truth table as given below: A

B

C

(A × B) × C

A × (B × C)

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 1

7

Since the last two columns of the truth table are identical, which proves that the AND operation is associative. (b) Since, A + B = B + A, therefore, OR operation is commutative. The associative property requires A + (B + C) = (A + B) + C which can be proved by making the truth table in a way similar to the truthtable of (a) above (c) Since, A Å B = B Å A, which means the EX-OR operation is commutative. The associative property requires (A Å B) Å C = A Å (B Å C) This can be proved by making truth table 1.15

(a) Since A B B A, therefore, the NAND operation is commutative. To verify whether the NAND operation is associative or not, we prepare the truth table as given below. From the Table we observe that the last two columns are not identical, which means A

B ( C ) (A B ) C This shows that the NAND operation is not associative. A

B

C

A (B C )

( A B) C

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

1 1 1 1 0 0 0 1

1 0 1 0 1 0 1 1

(b) Since, A

B

B

A , which means the NOR operation is commutative.

By making a truth table similar to the truth table of (a) above we can verify that

(A 1.16 1.17

B)

A (B

C

C)

Therefore, the NOR operation is not associative. Two possible realizations are given on page 9: (i) If only one of the variables is 1 and all others are zero, then (1 Å 0) Å 0 Å 0 Å . . . = 1 Å 0 Å 0 Å . . . =1 Å0=1 (ii) If only two of the variables are 1 and all others are zero, then (since EXOR operation is commutative and associative) (1 Å 1) Å 0 Å 0 Å 0 Å . . . = 0 Å 0 Å 0 Å 0 Å . . . = 0 (iii) Similarly, if only three of the variables are 1, then (1 Å 1) Å 1 Å 0 Å 0 Å . . . =0 Å1 Å0Å0 Å0 Å... =1 8

A

AÅB

B AÅBÅC C Y A ÅBÅ CÅD

D or A

AÅB

B Y A Å BÅ CÅ D

C D

CÅD Fig. 1.17

1.18

1.19

In the same way we can try higher number of ones. It is obvious from the above discussion that Z = 1, if an odd number of variables are 1 and Z = 0 if an even number of variables are 1. Since a logical variable can assume one of the two values (0 or 1) the number of possible combinations is 2N. Take an N-bit binary number bN–1 bN–2 . . . b2b1b0 and write all combinations from 00 . . . 000 to 11 . . . 111 in normal binary ascending order. (a) 7402 is a quad 2-input NOR gate. This means there are four identical 2-input NOR gates. Each gate requires three pins, two for inputs and one for output. Therefore, the four gates requires 3 ´ 4 = 12 pins. Two pins are required for the power supply (VCC and GND). Hence it is a 14-pin IC. (b) 7404 is a hex inverter. The number of pins = 2 ´ 6 + 2 = 14. (c) 7408 is a quad 2-input AND gate. The number of pins = 3 ´ 4 + 2 = 14. (d) 7410 is a triple 3-input NAND gate. The number of pins = 4 ´ 3 + 2 = 14. (e) 7411 is a triple 3-input AND gate. The number of pins = 4 ´ 3 + 2 = 14. (f) 7420 is a dual 4-input NAND gate. The number of pins = 5 ´ 2 + 2 = 12. Since 12-pin IC package is not used, therefore, it is packaged as 14-pin IC. Two pins are left free (NC). (g) 7427 is a triple 3-input NOR gate. The number of pins = 4 ´ 3 + 2 = 14. (h) 7432 is a quad 2-input OR gate. The number of pins = 3 ´ 4 + 2 = 14. 9

(i) 7486 is a quad EX-OR gate. The number of pins = 3 ´ 4 + 2 = 14. (a) (i) 7408 and 7432 (ii) 7400 (b) (i) 7432 and 7408 (ii) 7402 Logic Circuit A 0.4V = 0 2V = 1 Logic Circuit B –0.75V = 1 –1.55V = 0

1.20

1.21

1.22 Inputs

Output

A

B

C

AND Y1

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 1

1.23

OR Y2

NAND Y3

NOR Y4

0 1 1 1 1 1 1 1

1 1 1 1 1 1 1 0

1 0 0 0 0 0 0 0

Yes. (a)

A B C

(b)

A B C

Y

or

A B C

Y

Logic 1 Y

or

A B C

Y

Logic 0 (c)

A B C

Y

or

A B C

Y

Logic 1 (d)

A B C

Y

or

A B C Logic 0

10

Y

1.24

1.25 1.26 1.27

Yes. AND — by connecting one of the inputs to logic 0 OR — by connecting one of the inputs to logic 1 NAND — by connecting one of the inputs to logic 0 NOR — by connecting one of the inputs to logic 1. (a) Active-high (b) Active-low (c) Active-high (d) Active-low (a) Active-low (b) Active-high (c) Active-low (d) Active-high (a) A B Y C

Y = A × B × C = (A × B) × (C) (b)

A B Y C

Y = A + B + C = (A + B) + ( C) (c) A

AB

B

AB Y

C

Y

A B C

C

( A B)

C

( A B) C A B C

(d) A Y

B C 11

1.28

(a) A Å B = A B + A B A Å B = AB

(b) A

AB

= AB + AB = A Å B B = AB + AB

A Å B = AB

AB

= AB + AB

A Å B = AB A B AB AB (c) B Å (B Å AC) = B Å B Å AC = 0 Å AC = AC

12

CHAPTER 2 2.1 (a) 111001

= 1 ´ 25 + 1 ´ 24 + 1 ´ 23 + 0 ´ 22 + 0 ´ 21 + 1 ´ 20 = 32 + 16 + 8 + 0 + 0 + 1 = (57)10

(b) 101001

= 1 ´ 25 + 0 ´ 24 + 1 ´ 23 + 0 ´ 2 2 + 0 ´ 21 + 1 ´ 20 = 32 + 0 + 8 + 0 + 0 + 1 = (41)10

(c) 11111110 = 1 ´ 27 + 1 ´ 2 6 + 1 ´ 2 5 + 1 ´ 24 + 1 ´ 2 3 + 1 ´ 22 + 1 ´ 2 1 + 0 ´ 20 = 128 + 64 + 32 + 16 + 8 + 4 + 2 + 0 = (254)10 (d) 1100100

= 64 + 32 + 0 + 0 + 4 + 0 + 0 = (100)10

(e) 1101.0011 = 1 ´ 23 + 1 ´ 2 2 + 0 ´ 21 + 1 ´ 2 0 + 0 ´ 2 –1 + 0 ´ 2–2 + 1 ´ 2 –3 + 1 ´ 2–4 = 8 + 4 + 0 + 1 + 0 + 0 + 0.125 + 0.0625 = (13.1875)10 (f) 1010.1010 = 8 + 2 + 0.5 + 0.125 = (10.625)10 (g) 0.11100

= 0.5 + 0.25 + 0.125 = (0.875)10 Quotient

2.2 (a)

37 2 18 2 9 2 4 2 2 2 1 2

Remainder

18

1

9

0

4

1

2

0

1

0

0

1 1

Thus (37)10 = (100101)2 Similarly, (b) (255)10 = (11111111)2 (c) (15)10 = (1111)2 13

0

0

1

0

1

(d) Integer part: (26)10 = (11010)2 Fractional part: 0.25 0.5 ´2 ´2 0.5 1.0 ¯ ¯ 0 1 Therefore, (26.25)10 = (11010.01)2 (e) Integer part: (11)10 = (1011)2 Fractional part: 0.75 0.5 ´2 ´2 1.5 1.0 ¯ ¯ 1 1 Thus (11.75)10 = (1011.11)2 (f) 0.1 0.2 0.4 0.8 0.6 0.2 0.4 0.8 ´2 ´2 ´2 ´2 ´2 ´2 ´2 ´2 0.2 0.4 0.8 1.6 1.2 0.4 0.8 1.6 ¯ ¯ ¯ ¯ ¯ ¯ ¯ ¯ 0 0 0 1 1 0 0 1... Thus, (0.1)2 = (0.00011001)2 The process may be terminated at the required number of significant bits. 2.3 (a)

(b)

1

1

¬ Carry

1 0 +1 1 1 1 0  Final carry

1 0 0

1 1 0

1

1

1

1

1

1

1 0 + 1 1 0 0  Final carry

1 0 0

0. 1. 0.

1 0 0

¬ Carry 1 1 0

0

1

0

1

2.4 (a)

01000 –01001

01000 + 10111 (2’s complement) 11111 Since the MSB of the sum is 1, which means the result is negative and it is in 2’s complement form. 2’s complement of 11111 = 00001 = (1)10 Therefore, the result is –1.

14

(b)

(c)

01100 Þ 01100 –00011 + 11101 (2’s complement) 101001 = + 9  Ignore 0011.1001 Þ 0011.1001 –0001.1110 +1110.0010 (2’s complement) 10001.1011 = + 1.6875  Ignore

2.5 (a) 375 8 46 8 5 8

Quotient

Remainder

46

7

5

6

0

5

5 Therefore, (375)10 = (567)8 = (101110111)2 (b) Quotient Remainder 249 31 1 8 31 3 7 8 3 0 3 8 3

6

7

7

1

Therefore, (249)10 = (371)8 = (011111001)2 (c) Integer part: (27)10 = (33)8 = (011011)2 Fractional part: 0.125 ´8 1.000 ¯ 1 Thus (0.125)10 = (0.1)8 = (0.001)2 Therefore, (27.125)10 = (33.1)8 = (011011.001)2 2.6 (a) 11 011 100.101 010 = (334.52)8 (334.52)8 = 3 ´ 8 2 + 3 ´ 81 + 4 ´ 80 + 5 ´ 8 –1 + 2 ´ 8–2 = (220.65625)10 (b) 01 010 011.010 101 = (123.25)8 = (83.328125)10 (c) 10 110 011 = (263)8 = (179)10 15

2.7 (a) 375 16 23 16 1 16

Quotient

Remainder

23

7

1

7

0

1

1 7 7 Therefore, (375)10 = (177)16 (or 177H) = (0001 0111 0111)2 (b) Quotient Remainder 249 15 9 16 15 0 15 16 F 9 Therefore, (249)10 = (F9)16 (or F9H) = (1111 1001) 2 (c) Integer part: Quotient Remainder 27 1 11 16 1 0 1 16 1 B Thus (27)10 = 1BH Fractional part: 0.125 ´ 16 2.000 ¯ 2 \ (0.125)10 = 0.2H \ (27.125)10 = (1B.2)16 = 1B.2H = (00011011.0010)2 2.8 (a) 1101 1100.1010 10 = (DC.A8)16 (DC.A8)16 = 13 ´ 161 + 11 ´ 160 + 10 ´ 16–1 + 8 ´ 16–2 = (220.65625)10 (b) 0101 0011.0101 01 = (53.54)16 = (83.328125)10 (c) 1011 0011 = (B3)16 = (179)10 2.9 For each decimal digit write its natural BCD code (a) 46 = 0100 0110 (BCD) (b) 327.89 = 0011 0010 0111.1000 1001 (BCD) (c) 20.305 = 00100000.0011 0000 0101 (BCD) 2.10 For each decimal digit write its 4-bit Excess-3 code. (a) 46 = 0111 1001 (Excess-3) (b) 327.89 = 0110 0101 1010.1011 1100 (Excess-3) (c) 20.305 = 0101 0011.0110 0011 1000 (Excess-3) 16

2.11 Starting from 4-bit Gray code given in Table 2.8 formulate 5-bit Gray code as given below in Table 1. Table 1

Table 2

Decimal No.

G4

G3

G2

G1

G0

Decimal No.

G5

G4

G3

G2

G1

G0

0 1 2 : : 13 14 15 16 17 18 : : 29 30 31

0 0 0 : : 0 0 0 1 1 1 : : 1 1 1

0 0 0

0 0 1

0 1 1 3

0 0 0

0 0 1

0 1 1

1 1 0 0 1 1

1

1

0

0

1

1 1 1 1

0 0 0 0

0 0 0 0

0 0 0 0

1 0 0 1

1

1

0

0

1

0 0 0

0 0 0

1 0 0

1 1 0

0 0 0 0 0 0 0 0 0 1 1 1 ...