Modern Digital Electronics R. P. Jain PDF

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Scilab Textbook Companion for Modern Digital Electronics by R. P. Jain1 Created by Shikha Garg DIGITAL ELECTRONICS Instrumentation Engineering THAPAR UNIVERSITY College Teacher Mr. Sunil Kumar Singla Cross-Checked by

July 31, 2019

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Funded by a grant from the National Mission on Education through ICT, http://spoken-tutorial.org/NMEICT-Intro. This Textbook Companion and Scilab codes written in it can be downloaded from the ”Textbook Companion Project” section at the website http://scilab.in

Book Description Title: Modern Digital Electronics Author: R. P. Jain Publisher: Tata McGraw - Hill Education, New Delhi Edition: 4 Year: 2010 ISBN: 9780070669116

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Scilab numbering policy used in this document and the relation to the above book. Exa Example (Solved example) Eqn Equation (Particular equation of the above book) AP Appendix to Example(Scilab Code that is an Appednix to a particular Example of the above book) For example, Exa 3.51 means solved example 3.51 of this book. Sec 2.3 means a scilab code whose theory is explained in Section 2.3 of the book.

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Contents List of Scilab Codes

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1 Fundamental Concepts

5

2 Number System and Codes

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3 Semiconductor devices switching mode operation

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4 Digital Logic Families

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5 Combinational Logic Design

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6 Combinational Logic Design using MSI circuits

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7 Flip flops

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8 Sequential Logic Design

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9 Timing Circuits

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10 A to D and D to A Converters

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11 Semiconductor Memories

81

12 Programmable Logic Design

86 3

14 Computer Aided Design of Digital Systems

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87

List of Scilab Codes Exa Exa Exa Exa

1.1 1.3 1.7.a 1.7.b

Exa 1.9.a Exa 1.9.b Exa 1.11.a Exa 1.11.b Exa 1.13.a Exa 1.13.b Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa

2.1 2.2.a 2.2.b 2.2.c 2.2.d 2.3.a 2.3.b 2.3.c 2.3.d 2.4 2.5 2.6.a 2.6.b

And Gate . . . . . . . . . . . . . . . . . . . or gate . . . . . . . . . . . . . . . . . . . . . NAND gate . . . . . . . . . . . . . . . . . . NAND gate with one permanently connected to logic 1 . . . . . . . . . . . . . . . . . . . NOR gate connected to 0 logic as one input NOR gate with one input connected to logic 1 EXOR gate with one input permanently as logic 0 . . . . . . . . . . . . . . . . . . . . . EXOR gate with one input permanently as logic 1 . . . . . . . . . . . . . . . . . . . . . EXNOR gate with one input permanently as logic 0 . . . . . . . . . . . . . . . . . . . . . EXNOR gate with one input permanently as logic 1 . . . . . . . . . . . . . . . . . . . . . decimal equivalent . . . . . . . . . . . . . . conversion . . . . . . . . . . . . . . . . . . . conversion . . . . . . . . . . . . . . . . . . . conversion . . . . . . . . . . . . . . . . . . . conversion . . . . . . . . . . . . . . . . . . . decimal representation . . . . . . . . . . . . decimal representation . . . . . . . . . . . . decimal conversion . . . . . . . . . . . . . . decimal representation . . . . . . . . . . . . binary conversion . . . . . . . . . . . . . . . conversion . . . . . . . . . . . . . . . . . . . dec to bin . . . . . . . . . . . . . . . . . . . dec to bin . . . . . . . . . . . . . . . . . . . 5

5 5 6 7 7 7 8 8 9 9 10 10 11 11 11 12 13 15 17 19 19 20 22

Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa Exa

2.6.c 2.8.a 2.8.b 2.9.a 2.9.b 2.9.c 2.10.a 2.10.b 2.11.a 2.11.b 2.11.c 2.11.d 2.13.a 2.13.b 2.14 2.15 2.16 2.17 2.21 2.22 2.23 2.26 2.27.a 2.27.b 2.30 2.31 2.33 2.35 2.36.a 2.36.b 3.3 3.4.a 3.4.b 3.5.a 3.5.b 3.7.a 3.7.b

dec to bin . . . . . . . . . . . . . . . . . . . ones complement . . . . . . . . . . . . . . . ones complement of unsigned no . . . . . . . ones comp . . . . . . . . . . . . . . . . . . . ones complement of signed no . . . . . . . . ones complement of signed no . . . . . . . . twos complement . . . . . . . . . . . . . . . twos complement of binary no . . . . . . . . complement . . . . . . . . . . . . . . . . . . complement . . . . . . . . . . . . . . . . . . complement . . . . . . . . . . . . . . . . . . twos complement of binary number . . . . . addition . . . . . . . . . . . . . . . . . . . . addition of binary numbers . . . . . . . . . addition of 4 binary numbers . . . . . . . . subtraction of binary numbers . . . . . . . . multiplication of binary numbers . . . . . . division of binary numbers . . . . . . . . . . decimal to octal conversion . . . . . . . . . convert octal to binary . . . . . . . . . . . . binary to octal . . . . . . . . . . . . . . . . addition of octal numbers . . . . . . . . . . addition of octal numbers . . . . . . . . . . addition of OCTAL numbers . . . . . . . . . convert hexadecimal to binary . . . . . . . . binary to hexadecimal number . . . . . . . . hexadecimal to octal number . . . . . . . . addition of hexadecimal numbers . . . . . . subtraction of hexadecimal numbers . . . . subtraction of hexadecimal numbers . . . . response of transistor inverter . . . . . . . . output voltage of JFET . . . . . . . . . . . output voltage of JFET . . . . . . . . . . . output characateristics of a MOSFET . . . . output voltage for MOSFET . . . . . . . . . output voltage for identical set of transistors output voltage in identical transistors for input voltage 5V . . . . . . . . . . . . . . . . 6

23 24 25 25 26 27 28 28 29 30 30 31 32 32 33 34 34 35 36 36 37 37 38 39 40 40 41 41 42 43 44 45 46 46 47 47 48

Exa 4.1.a.i Exa 4.1.a.ii

calculate fan out when all inputs are high . 49 calculate fan out for DTL NAND gate when 50 atleast one input is LOW . . . . . . . . . . Exa 5.1 simplification of equation . . . . . . . . . . . 52 Exa 5.2 conversion to canonical SOP form . . . . . . 53 Exa 5.3 conversion to canonical POS form . . . . . . 53 Exa 6.1 boolean equation using 8 to 1 mux . . . . . 55 Exa 6.4.a subtraction . . . . . . . . . . . . . . . . . . 57 Exa 6.4.b subtraction . . . . . . . . . . . . . . . . . . 60 Exa 6.5.a.i 8 bit adder . . . . . . . . . . . . . . . . . . 62 Exa 6.5.a.ii 8 bit subtractor . . . . . . . . . . . . . . . . 64 Exa 6.5.b.i 8 bit adder . . . . . . . . . . . . . . . . . . 67 Exa 6.5.b.ii 8 bit subtractor . . . . . . . . . . . . . . . . 69 Exa 7.1 clocked SR flip flop . . . . . . . . . . . . . . 72 Exa 7.2 convert SR flip flop to JK flip flop . . . . . . 73 Exa 8.2 maximum frequency . . . . . . . . . . . . . 74 Exa 9.3 Schmitt trigger . . . . . . . . . . . . . . . . 75 Exa 10.1 find analog output of 4 bit D to A converter 76 Exa 10.2.a 4 bit unipolar D to A converter . . . . . . . 77 Exa 10.2.b 4 bit unipolar D to A converter after adjusting the offset voltage . . . . . . . . . . . . . . . 77 Exa 10.2.c 4 bit unipolar D to A converter after compli78 menting MSB . . . . . . . . . . . . . . . . . Exa 10.3 D to A converter in ones complement form . 79 Exa 10.4 2 decade BCD D to A converter . . . . . . . 79 Exa 10.5 determine the quantization interval . . . . . 80 Exa 11.1 Binary address of each location of size 16 words 81 Exa 11.2.a maximum rate at which data can be stored . 82 Exa 11.2.b maximum rate at which data can be read . . 82 Exa 11.6.a data output . . . . . . . . . . . . . . . . . . 83 Exa 11.6.b data output . . . . . . . . . . . . . . . . . . 83 Exa 11.6.c data output . . . . . . . . . . . . . . . . . . 84 Exa 11.6.d data output . . . . . . . . . . . . . . . . . . 84 Exa 11.7.a output and change in memory location . . . 85 Exa 12.1 find the product term . . . . . . . . . . . . 86 Exa 14.2 entity construction for EXOR circuit . . . . 87

7

Chapter 1 Fundamental Concepts

Scilab code Exa 1.1 And Gate // ex a m p l e 1 . 1 / / clc // c l e a r s t h e s c r e e n // clear // c l e a r s t h e e x i s t i n g v a r i a b l e s // disp ( ’ t h e l o c k e r d o or (Y) c a n be op en ed u s i n g on e key (A) w h i c h i s w i th you and t h e o t h e r k ey (B) wh i c h i s w i t h t h e bank e x e c u t i v e . When b ot h t h e k ey s a re u sed , t h e l o c k e r d o or op en s , i . e . t h e l o c k e r d o or c a n be op en ed (Y=1) o n l y when bot h t h e k e y s a r e a p p l i e d (A=B=1) . Thus , t h i s ca n b e e x p r e s s e d a s an AND o p e r a t i o n ’ ) 7 disp ( ’Y=A∗B ’ ) 1 2 3 4 5 6

Scilab code Exa 1.3 or gate 8

// ex a m p l e 1 . 3 / / clc // c l e a r s t h e s c r e e n // clear // c l e a r s a l r e a d y e x i s t i n g v a r i a b l e s // disp ( ’ Le t t h e t e m p e r a t u r e and p r e s s u r e be c o n v e r t e d i n t o e l e c t r i c a l s i g n a l s and T=1 i f t e m p e r a t u r e e x c e e d s t h e s p e c i f i e d l i m i t and P=1 i f p r e s s u r e e x c e e d s t h e s p e c i f i e d l i m i t . I f T=1 or P=1 o r b ot h T and P a r e 1 t h e n t h e al a rm i s r e q u i r e d t o be a c t i v a t e d , i . e . , t h e s i g n a l a p p l i e d t o t h e a l a rm Y=1. T hi s o p e r a t i o n c an be e x p r e s s e d a s an or o p e r a t i o n . ’ ) 7 disp ( ’Y=T o r P ’ ) 8 disp ( ’Y=T+P ’ ) 1 2 3 4 5 6

Scilab code Exa 1.7.a NAND gate // ex a m p l e 1 . 7 ( a ) // clc // c l e a r s t h e s c r e e n // clear // c l e a r s a l r e a d y e x i s t i n g v a r i a b l e s // disp ( ’ when on e o f t h e l o g i c i n p u t o f 2− i n p u t NAND g a t e i s 0 , t h en i r r e s p e c t i v e o f t h e o t h e r i n p u t , t h e ou t p u t com es ou t t o b e 1 . I n f a c t , a NAND g a t e i s d i s a b l e d or i n h i b i t e d i f on e o f i t s in p u t s i s connect ed to l o g i c 0 ’ ) 7 disp ( ’Y=1 ’ ) 1 2 3 4 5 6

9

Scilab code Exa 1.7.b NAND gate with one permanently connected to logic 1 // ex a m p l e 1 . 7 ( b ) // clc // c l e a r s t h e s c r e e n // clear // c l e a r s a l r e a d y e x i s t i n g v a r i a b l e s // disp ( ’ when on e o f t h e l o g i c i n p u t o f 2− i n p u t NAND g a t e i s 1 , t h en when A=1 , Y=0 and i f A=0 , Y=1 ’ ) 7 disp ( ’Y=A ’ ’ ’ )

1 2 3 4 5 6

Scilab code Exa 1.9.a NOR gate connected to 0 logic as one input // ex a m p l e 1 . 9 ( a ) // clc // c l e a r s t h e s c r e e n // clear // c l e a r s a l r e a d y e x i s t i n g v a r i a b l e s // disp ( ’ when on e o f t h e l o g i c i n p u t o f 2− i n p u t NOR g a t e i s 0 , t h en when A=1 , Y=0 and i f A=0 , Y=1 ’ ) 7 disp ( ’Y=A ’ ’ ’ ) 1 2 3 4 5 6

Scilab code Exa 1.9.b NOR gate with one input connected to logic 1 10

// ex a m p l e 1 . 9 ( b ) // clc // c l e a r s t h e s c r e e n // clear // c l e a r s a l r e a d y e x i s t i n g v a r i a b l e s // disp ( ’ when on e o f t h e l o g i c i n p u t o f 2− i n p u t NOR g a t e i s 1 , t h en i r r e s p e c t i v e o f t h e o t h e r i n p u t , t h e ou t p u t com es ou t t o b e 0 . I n f a c t , a NAND g a t e i s d i s a b l e d or i n h i b i t e d i f on e o f i t s in p u t s i s connect ed to l o g i c 1 ’ ) 7 disp ( ’Y=0 ’ ) 8 disp ( ’ h e r e t h e o u t p u t o f Y i s 0 i r r e s p e c t i v e o f input of A’) 1 2 3 4 5 6

Scilab code Exa 1.11.a EXOR gate with one input permanently as logic 0 // ex a m p l e 1 . 1 1 ( a ) // clc // c l e a r s t h e s c r e e n // clear // c l e a r s a l r e a d y e x i s t i n g v a r i a b l e s // disp ( ’ I f we c o n n e c t on e i n p u t o f EX−OR g a t e t o 0 p e rm a n e nt l y , we o b s e r v e t h a t Y=A∗0 ’ ’+A ’ ’ ∗0 ’ ) 7 disp ( ’ t h u s , Y=A ’ )

1 2 3 4 5 6

Scilab code Exa 1.11.b EXOR gate with one input permanently as logic 1 1 2

// ex a m p l e 1 . 1 1 ( b ) // clc 11

// c l e a r s t h e s c r e e n // clear // c l e a r s a l r e a d y e x i s t i n g v a r i a b l e s // disp ( ’ I f we c o n n e c t on e i n p u t o f EX−OR g a t e t o 1 p e rm a n e nt l y , we o b s e r v e t h a t Y=A∗1 ’ ’+A ’ ’ ∗1 ’ ) 7 disp ( ’ t h u s , Y=A ’ ’ ’ ) 3 4 5 6

Scilab code Exa 1.13.a EXNOR gate with one input permanently as logic 0 // ex a m p l e 1 . 1 3 ( a ) // clc // c l e a r s t h e s c r e e n // clear // c l e a r s a l r e a d y e x i s t i n g v a r i a b l e s // disp ( ’ I f we c o n n e c t on e i n p u t o f EX−NOR g a t e t o 0 p e rm a n e nt l y , we o b s e r v e t h a t Y=A∗0+A ’ ’ ∗0 ’ ’ ’ ) 7 disp ( ’ t h u s , Y=A ’ ’ ’ )

1 2 3 4 5 6

Scilab code Exa 1.13.b EXNOR gate with one input permanently as logic 1 // ex a m p l e 1 . 1 3 ( b ) // clc // c l e a r s t h e s c r e e n // clear // c l e a r s a l r e a d y e x i s t i n g v a r i a b l e s // disp ( ’ I f we c o n n e c t on e i n p u t o f EX−NOR g a t e t o 1 p e rm a n e nt l y , we o b s e r v e t h a t Y=A∗1+A ’ ’ ∗1 ’ ’ ’ ) 7 disp ( ’ t h u s , Y=A ’ )

1 2 3 4 5 6

12

Chapter 2 Number System and Codes

Scilab code Exa 2.1 decimal equivalent 1 2 3 4 5 6

// ex a m p l e 2 . 1 / / // d ec i m a l t o b i n a r y c o n v e r s i o n // ans = bin2dec ( ’ 111 11 ’ ) // d e c i m a l e q u i v a l e n t o f b i n a r y number // disp ( ans ) // a ns w er i n d e c i m a l fo rm //

Scilab code Exa 2.2.a conversion 1 2 3 4 5 6

// ex a m p l e 2 . 2 ( a ) // // d ec i m a l t o b i n a r y c o n v e r s i o n // ans = bin2dec ( ’ 11 010 1 ’ ) // d e c i m a l e q u i v a l e n t o f b i n a r y number // disp ( ans ) // a ns w er i n d e c i m a l fo rm //

13

Scilab code Exa 2.2.b conversion 1 2 3 4 5 6

// ex a m p l e 2 . 2 ( b ) // // d ec i m a l t o b i n a r y c o n v e r s i o n // ans = bin2dec ( ’ 10 110 1 ’ ) // d e c i m a l e q u i v a l e n t o f b i n a r y number // disp ( ans ) // a ns w er i n d e c i m a l fo rm //

Scilab code Exa 2.2.c conversion 1 2 3 4 5 6

// ex a m p l e 2 . 2 ( c ) // // d ec i m a l t o b i n a r y c o n v e r s i o n // ans = bin2dec ( ’ 1 11 11 11 1 ’ ) // d e c i m a l e q u i v a l e n t o f b i n a r y number // disp ( ans ) // a ns w er i n d e c i m a l fo rm //

Scilab code Exa 2.2.d conversion 1

// ex a m p l e 2 . 2 ( d ) // 14

2 3 4 5 6

// d ec i m a l t o b i n a r y c o n v e r s i o n // ans = bin2dec ( ’ 0 00 00 00 0 ’ ) // d e c i m a l e q u i v a l e n t o f b i n a r y number // disp ( ans ) // a ns w er i n d e c i m a l fo rm //

Scilab code Exa 2.3.a decimal representation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

// ex a m p l e 2 . 3 ( a ) // clc // c l e a r s t h e command window // clear // c l e a r s // p =1; // i n i t i a l i s i n g // q =1; z =0; b =0; w =0; f =0; // b i n= i n p u t ( E nt er t h e b i n a r y no t o be c on v er t ed t o i t s d ec im a l eq u i v a l en t : ) // a c c e p t i n g t h e b i n a r y i n p u t f rom u s e r // b in = 1 0 1 1 0 1 . 1 0 1 0 1 ; d = modulo ( bin ,1) ; // s e p a r a t i n g t h e d e c i m a l p a r t and t h e i n t e g e r p a r t // d = d * 10 ^1 0; a = floor ( bin ) ; // r em o vi n g t h e d e c i m a l p a r t // while ( a >0) // Loop t o t a k e t h e b i n a r y b i t s o f i n t e g e r i n t o a m a t r i x // r = modulo ( a ,10) ; b (1 , q ) = r ; a = a /10; 15

26 a = floor ( a ) ; 27 q = q +1; 28 end 29 for m =1: q -1 30 // m u l t i p l i y i n g t h e b i t s 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

o f i n t e g e r wit h t h e i r p o s i t i o n v a l u e s and a d d i n g // c = m -1; f = f + b (1 , m ) *(2^ c ); end while ( d >0) // Loop t o t a k e t h e b i n a r y b i t s o f d e c i m a l i n t o a m a t r i x // e = modulo ( d ,2) w (1 , p ) = e d = d /10; d = floor ( d ) p = p +1; end for n =1: p -1 // m u l t i p l i y i n g t h e b i t s o f d e c i m a l w i t h t h e i r p o s i t i o n v a l u e s and a d d i n g // z = z + w (1 , n ) *( 0. 5) ^(11 - n ) ; end z = z *10000; // r o u n d i n g o f t o 4 d e c i m a l v a l u e s // z = round ( z ) ; z = z /10000; x=f+z; disp ( ’ The D e c i m a l e q u i v a l e n t o f t h e B i n a r y number giv en i s ’); disp ( x ) ; // D i s p l a y i n g t h e f i n a l r e s u l t //

16

Scilab code Exa 2.3.b decimal representation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33

// ex a m p l e 2 . 3 ( b ) // clc // c l e a r s t h e command window // clear // c l e a r s // p =1; // i n i t i a l i s i n g // q =1; z =0; b =0; w =0; f =0; // b i n= i n p u t ( E nt er t h e b i n a r y no t o be c on v er t ed t o i t s d ec im a l eq u i v a l en t : ) // a c c e p t i n g t h e b i n a r y i n p u t f rom u s e r // bin =1 1 00 . 10 1 1 ; d = modulo ( bin ,1) ; // s e p a r a t i n g t h e d e c i m a l p a r t and t h e i n t e g e r p a r t // d = d * 10 ^1 0; a = floor ( bin ) ; // r em o vi n g t h e d e c i m a l p a r t // while ( a >0) // Loop t o t a k e t h e b i n a r y b i t s o f i n t e g e r i n t o a m a t r i x // r = modulo ( a ,10) ; b (1 , q ) = r ; a = a /10; a = floor ( a ) ; q = q +1; end for m =1: q -1 // m u l t i p l i y i n g t h e b i t s o f i n t e g e r w i t h t h e i r p o s i t i o n v a l u e s and a d d i n g // c = m -1; f = f + b (1 , m ) *(2^ c ); end 17

34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

while ( d >0) // Loop t o t a k e t h e b i n a r y b i t s o f d e c i m a l i n t o a m a t r i x // e = modulo ( d ,2) w (1 , p ) = e d = d /10; d = floor ( d ) p = p +1; end for n =1: p -1 // m u l t i p l i y i n g t h e b i t s o f d e c i m a l w i t h t h e i r p o s i t i o n v a l u e s and a d d i n g // z = z + w (1 , n ) *( 0. 5) ^(11 - n ) ; end z = z *10000; // r o u n d i n g o f t o 4 d e c i m a l v a l u e s // z = round ( z ) ; z = z /10000; x=f+z; disp ( ’ The D e c i m a l e q u i v a l e n t o f t h e B i n a r y number giv en i s ’); disp ( x ) ; // D i s p l a y i n g t h e f i n a l r e s u l t //

Scilab code Exa 2.3.c decimal conversion 1 // ex a m p l e 2 . 3 ( c ) // 2 clc 3 // c l e a r s t h e command window // 4 clear 5 // c l e a r s // 6 p =1; 7 // i n i t i a l i s i n g //

18

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

q =1; z =0; b =0; w =0; f =0; // b i n= i n p u t ( E nt er t h e b i n a r y no t o be c on v er t ed t o i t s d ec im a l eq u i v a l en t : ) // a c c e p t i n g t h e b i n a r y i n p u t f rom u s e r // bin =1 0 01 . 01 0 1 ; d = modulo ( bin ,1) ; // s e p a r a t i n g t h e d e c i m a l p a r t and t h e i n t e g e r p a r t // d = d * 10 ^1 0; a = floor ( bin ) ; // r em o vi n g t h e d e c i m a l p a r t // while ( a >0) // Loop t o t a k e t h e b i n a r y b i t s o f i n t e g e r i n t o a m a t r i x // r = modulo ( a ,10) ; b (1 , q ) = r ; a = a /10; a = floor ( a ) ; q = q +1; end for m =1: q -1 // m u l t i p l i y i n g t h e b i t s o f i n t e g e r w i t h t h e i r p o s i t i o n v a l u e s and a d d i n g // c = m -1; f = f + b (1 , m ) *(2^ c ); end while ( d >0) // Loop t o t a k e t h e b i n a r y b i t s o f d e c i m a l i n t o a m a t r i x // e = modulo ( d ,2) w (1 , p ) = e d = d /10; d = floor ( d ) p = p +1; end 19

42 43 44 45 46 47 48 49 50 51 52 53

for n =1: p -1 // m u l t i p l i y i n g t h e b i t s o f d e c i m a l w i t h t h e i r p o s i t i o n v a l u e s and a d d i n g // z = z + w (1 , n ) *( 0. 5) ^(11 - n ) ; end z = z *10000; // r o u n d i n g o f t o 4 d e c i m a l v a l u e s // z = round ( z ) ; z = z /10000; x=f+z; disp ( ’ The D e c i m a l e q u i v a l e n t o f t h e B i n a r y number given i s ’); disp ( x ) ; // D i s p l a y i n g t h e f i n a l r e s ...