MP unit test2 - HELPFUL FOR STUDENTS PDF

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HELPFUL FOR STUDENTS...

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In the executable segment descriptor the conforming bit comes under * 1 point Limit Type// Base Offset The linear address is calculated by * effective address + segment base address// effective address –segment base address effective address + physical address effective address –physical address If the paging unit is enabled, then it converts linear address into * Effective address physical address// segment base address none of the mentioned If the paging unit is disabled, then the linear address is used as * effective address physical address// segment base address none of the mentioned The paging unit is enabled only in * virtual mode addressing mode protected mode// none of the mentioned The bit that indicates whether the segment has been accessed by the CPU or not is * base address attribute bit// present bit granular bit If the segment descriptor bit, S=0, then the descriptor is * data segment descriptor code segment descriptor system descriptor// all of the mentioned The bit that indicates whether the segment is page addressable is * base address attribute bit present bit granularity bit// The segment descriptor contains * access rights limit base address all of the mentioned//

Which of the following is not a type of segment descriptor? * system descriptors local descriptors gate descriptors none // The limit field of the descriptor is of * 10 bits 8 bits 16 bits 20 bits// The total descriptors that the 80386 can handle is * 2K 8K 4K 16K// The page table cache is also known as * page table storage b) storage buffer// c) translation look aside buffer all of the mentioned Call gate descriptor may reside in * GDT LDT IDT Both GDT and LDT// Task can be restricted to cause task switch with task gate available at * GDT GDT / LDT IDT LDT// The Applications are related with __________ privilege level * 1 point Level 0 Level 1 Level 2 Level 3// The privilege level of the code segment determines the * DPL RPL CPL// IOPL Which of the following is not protection aspect of 80386 * Restriction of addressable domain Restriction of interrupt entry point// Restriction of procedure entry points Restriction of instruction set

For a single task in protected mode, the 80386 can address the virtual memory of * 32 GB 64 MB 32 TB 64 TB// The bit that is used for providing protection is * User/Supervisor bit Read bit Write bit all of the mentioned// What are the different levels of security in 80386 ? * Task level security Page level security Segment level security Both b & c /// The mechanism that is executed at certain privilege levels, determined by CPL (Current Privilege Level) and I/O pri vilege level (IOPL) is * restricted use of segments restricted accesses to segments privileged instructions or operations// none of the mentioned Which is the highest and most secure privilege level in 80386 ? * Privilege Level 0// Privilege Level 1 Privilege Level 2 Privilege Level 3 What is the privilege level of Kernal in Operating System ? * Privilege level 2 Privilege level 1 Privilege level 3 Privilege level 0// What fields are checked by Privilege check unit of CPU ? * CPL RPL DPL All of the above.// To change I/O permission, you must be running at privilege level * CPL>DPL CPL...