Notes - Lecture - Chapter 10 PDF

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Notes on chapter 10...

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DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING, THE UNIVERSITY OF NEW MEXICO ECE-238L: Computer Logic Design

Fall 2013

Notes - Chapter 10 BASIC COMPUTER ARCHITECTURES Computer: Processor + I/O + memory Harvard vs. Von Neumann Harvard: - Instruction memory and data memory - Operands usually placed in registers in the CPU: register-register architecture Von Neumann: - One memory for both instruction and data - Operands placed in a dedicated register called accumulator or in the instruction memory: registermemory architecture VCB1- computer: Harvard Computer: Only one instruction memory. No data memory.

CONTROL UNIT

IN

DATAPATH UNIT IR[3..0] 4 1

4

0

M3 M6

1

0

1

0

0000

M1

cin

+ 4

L_R0

L_R1 E

R0

IR[3..0]

E

R1

0

M4

S_EN STEP

R1

R0

1

0

PC 4

1

M2 WE

M5

IR[7..5]

IR[7..0]

E

1

Instruction Memory (16x8)

0 4

D[7..0]

4

ALU

loadi addi add sr0

L_OP

E

IR[7..0]

OUT 4 LEDS

R0

0

R1

1

z

INSTRUCTION DECODER

IR[4]

M1 M2 M3 M4 M5 M6 L_R0 L_R1 L_OP

Instructor: Daniel Llamocca

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING, THE UNIVERSITY OF NEW MEXICO ECE-238L: Computer Logic Design

Fall 2013

Available Registers: R0(register 0), R1(register 1), PC(program counter), IR(instruction register), OUT (output register) Instruction Set: Instructions are specified on the Instruction Register (IR): Destination Register Source Register

OPCODE DR

SR

IR: IMMEDIATE DATA

DR=0  R0 is the destination register, DR=1  R1 is the destination register. SR=0  R0 is the source register, SR=1  R1 is the source register. OPCODE: IR[7..5] DATA: IR[3..0] OPCODE (IR[7..5])

Instruction

000 001 010 011 100 101 110

MOV DR, SR LOADI DR, DATA ADD DR, SR ADDI DR, DATA SR0 DR, SR IN DR OUT DR

Operation

111

JNZ DR, ADDRESS

DR  SR DR  DATA, DATA = IR[3..0] DR  DR + SR DR  DR + DATA, DATA = IR[3..0] DR  0&SR[3..1] DR  IN OUT  DR PC  PC + 1 if DR=0 PC  IR[3..0] if DR0 * ADDRESS = IR[3..0]

Executing Instructions:  IN DR: DR grabs the contents from the input 0 1

1

0

1

DR

X

X

X

X

X

X

X

X

X

X

IN R0: 1010XXXX  M1  1, L_R0  1, M6  0 IN R1: 1011XXXX  M1  1, L_R1  1, M6  0

 OUT DR: Places the contents of DR on the output register 0 1

1

1

0

DR

X

OUT R0: 1100XXXX  M2  0, L_OP  1, M6  0 OUT R1: 1101XXXX  M2  1, L_OP  1, M6  0

 MOV DR, SR: Copies the contents of SR onto DR 0 1

0 MOV R0, MOV R1, MOV R0, MOV R1,  "MOV

R0: 00000XXX R1: 00011XXX R1: 00001XXX R0: 00010XXX R0,R0", "MOV

0

 M2  0,  M2  1,  M2  1,  M2  0, R1,R1"(can

0 M3 M3 M3 M3 be

DR

0 1

SR

 0, M1  0, L_R0  1,  0, M1  0, L_R1  1,  0, M1  0, L_R0  1,  0, M1  0, L_R1  1, used as NOP instruction)

M6 M6 M6 M6

   

0 0 0 0

Instructor: Daniel Llamocca

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING, THE UNIVERSITY OF NEW MEXICO ECE-238L: Computer Logic Design

Fall 2013

 LOADI DR, DATA: Copies immediate DATA onto DR 0 1

0

0

1

DR

d3

d2

d1

d0

LOADI R0, DATA: 0010d3d2d1d0  M5  1, M3  1, M1  0, L_R0  1, M6  0 LOADI R1, DATA: 0011d3d2d1d0  M5  1, M3  1, M1  0, L_R1  1, M6  0

 ADDI DR, DATA: Adds immediate DATA and DR, and copies the result onto DR 0 1

0

1

1

DR

d3

d2

d1

d0

 M2  0, M5  1, M3  1, M1  0, L_R0  1, M6  0 ADDI R1, DATA: 0111d3d2d1d0  M2  1, M5  1, M3  1, M1  0, L_R1  1, M6  0

ADDI R0, DATA: 0110d3d2d1d0

 ADD DR, SR: Adds SR and DR, and copies the result onto DR 0 1

0

1

   ADD R1,R1: 01011XXX 

0

DR

0 1

SR

X

X

X

ADD R0,R0: 01000XXX

M40, M50, M20, M31, M10, L_R01, M60

ADD R0,R1: 01001XXX ADD R1,R0: 01010XXX

M40, M50, M21, M31, M10, L_R01, M60 M40, M50, M21, M31, M10, L_R11, M60 M41, M50, M21, M31, M10, L_R11, M60

 SR0 DR, SR: Shifts (to the right) the contents of SR and places the result onto DR 0 1

1

0

   SR0 R1,R1: 10011XXX 

0

DR

0 1

SR

X

X

X

SR0 R0,R0: 10000XXX

M40, M50, M20, M31, M10, L_R01, M60

SR0 R0,R1: 10001XXX SR0 R1,R0: 10010XXX

M40, M50, M21, M31, M10, L_R01, M60 M40, M50, M21, M31, M10, L_R11, M60 M41, M50, M21, M31, M10, L_R11, M60

 JNZ DR, ADDRESS 1: if R=0

0 1

1

1

1

DR

a3

a2

a1

a0

R0

0

R1

1

R

z 0: if R0

IR[4]

JNZ R0, ADDRESS: 1110a3a2a1a0 JNZ R1, ADDRESS: 1111a3a2a1a0

 M6  0 if z = 1, M6  1 if z = 0  M6  0 if z = 1, M6  1 if z = 0

Keep in mind:   

The input IR[7..5] takes care automatically of the correct operation at the ALU. M6  0 means that PC  PC + 1 M6  1 means PC  IR[3..0]

Instructor: Daniel Llamocca...