Place and Route using Synopsys IC Compiler Cornell PDF

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Place and Route using Synopsys IC Compiler ECE5745 Tutorial 3 (Version 606ee8a) January 30, 2016 Derek Lockhart

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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Getting The Tutorial Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Important Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual IC Compiler Build Process . . . . . . . . . . . . . . . . . . . . . . . . . . Automated IC Compiler Build Process . . . . . . . . . . . . . . . . . . . . . . . . Interpreting the Place and Route Reports . . . . . . . . . . . . . . . . . . . . . . Using the IC Compiler GUI to Analyze Place and Route . . . . . . . . . . . . . Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Introduction

In this tutorial you will gain experience using Synopsys IC Compiler (ICC). ICC takes a and as input, then . Figure 1 illustrates the basic ICC toolflow and how it fits into the larger ECE5745 flow. The first goal of a Place and Route (P&R) tool is to determine where each gate should be located on the physical chip (the placement portion of place and route). This process leverages heuristic algorithms to group related gates together in hopes of minimizing routing congestion and wire delay. Typically P&R tools will focus their effort on minimizing the delay through the critical path, and to this end will resize gates, insert new buffers, and even perform local resynthesis. Additionally, P&R tools often have secondary algorithms to help reduce area for non-critical paths. After placement, ICC will attempt to route the design while minimizing wire delay. Along with routing, P&R tools often handle clock tree synthesis, power routing, and block level floorplanning. For this tutorial we will generate layout for the gate-level netlist of the greatest common divisor (GCD) circuit synthesized in Tutorial 2. Once the netlist has successfully been placed and routed, you should be able to see all the instantiated standard cells and routed metals of the physical implementation. We will then use the IC Compiler GUI to visualize the layout of your final placed and routed design. Note that this tutorial is by no means comprehensive. Synopsys documentation is located on the public course webpage (http://www.csl.cornell.edu/courses/ece5745/syndocs) and can be accessed using the username and password distributed in lecture.

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Getting The Tutorial Code

All of the ECE5745 tutorials should be run on the BRG compute servers brg-01.ece.cornell.edu and brg-02.ece.cornell.edu. Before proceeding further, please log into one of these machines. You should follow along through the tutorial yourself by typing in the commands marked with a ’%’ symbol at the shell prompt. To cut and paste commands from this tutorial into your bash shell (and make sure bash ignores the ’%’ character) use an alias to ”undefine” the ’%’ character:

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Figure 1: IC Compiler Toolflow

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% alias %="" Once you have logged into a BRG machine you will need to setup the ECE5745 toolflow with the following commands: % source setup-ece5745.sh For this tutorial you will be using a GCD circuit as your example RTL design. If you don’t already have the source files from the previous tutorials, create an ece5745 folder in your home directory and clone the tutorial files from the git repository: % % % % %

mkdir ${HOME}/ece5745 cd ${HOME}/ece5745 git clone [email protected]:cornell-ece5745/ece5745-tut-asic.git cd ece5745-tut-asic/tutorial TUTROOT=$PWD

Before starting, take a look at the subdirectories in the project directory. Note that there are directories for your RTL source (src) and for generated content (build). The build directory has subdirectories for each major step in the ECE5745 toolflow, these subdirectories contain scripts and configuration files necessary for running the tools. For this tutorial you will work exclusively in the icc-par subdirectory.

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Important Files

Like Design Compiler, IC Compiler is an extremely complicated tool that requires many pieces to work correctly. Attempts at synthesis without providing the tools with properly formatted configuration scripts, constraint information, and numerous technology files for the target standard cells will only be met with more pain and sadness. Below is a list of important library files needed by the place and route tool. Note that these files are identical to those required by the DC synthesis tool. As mentionined in Tutorial 2, these files are specific to the Synopsys 90nm Educational Library and need to be changed when targeting a different standard cell library or process. • cells.db - Synopsys 90nm digital standard cell model library. Contains timing and area information for each standard cell. • cells cg.db - Additional standard cell models for clock gating cells. • milkyway.fr - Milkyway Reference database for the 90nm standard cell library. Contains wireload models for the standard cells. • techfile.tf - Technology file containing charactersitics and design rules for the 90nm process. • tech2itf.map - Technology to ITF (interconnect technology) mapping file. • max.tluplus - Models containing advanced process effects. • min.tluplus - Models containing advanced process effects. In addition to the Synopsys 90nm Library files, the place and route tools require two additional inputs: a gate-level netlist and a Synopsys design constraint file. Both of these files are generated by the synthesis tool. • your design.mapped.v - Gate-level netlist. • your design.mapped.sdc - Gate-level constraints file.

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Manual IC Compiler Build Process

We will first go through the commands for the tool manually on the commandline so that you can see all the different steps that are required to make the tool work. Since this is extremely tedious, we will only do this once, and later we will use scripts to automate the steps in this portion of the flow for us. ICC can generate a large number of output files so you will be running ICC within a build directory beneath icc-par. Use the following commands to create a build directory for IC Compiler and to start the ICC GUI (note that you will need an X session): % % % %

cd $TUTROOT/build/icc-par mkdir manual cd manual icc_shell -64bit -gui

In addition to being left at the ICC shell prompt, the ICC GUI window should have popped up. You can either enter ICC commands via the ICC shell prompt in your terminal or in the command bar at the bottom of the ICC GUI, but from our experience the terminal is usually easier. Note that you can always get more information about a specific command by entering man at the icc shell prompt. Execute the following commands manually in the ic shell> prompt. The first command will create an alias to ”undefine” the ic shell> string, which will allow you to cut and paste commands from this tutorial into IC Compiler. Also be sure to keep an eye on the GUI as you enter these commands, IC Compiler will update the display of your design as cells are placed and wires are routed. # Create an alias for copy and paste. icc_shell> alias "icc_shell>" "" # Execute some commands to setup your environment. icc_shell> icc_shell> icc_shell> icc_shell>

set stdcells_home /research/brg/install/bare-pkgs/noarch/synopsys-90nm/toolflow set_app_var search_path "$stdcells_home" set_app_var target_library "cells.db" set_app_var link_library "* $target_library"

# Create your own Milkyway database where the placed & routed design will be saved. # Needs the technology file (information about the process - poly and metal layers) # and the Milkyway reference database (contains standard cell layout). icc_shell> create_mw_lib \ -tech "$stdcells_home/techfile.tf" \ -bus_naming_style {[%d]} \ -mw_reference_library "$stdcells_home/milkyway.fr" \ "gcdGCDUnit_rtl_LIB" icc_shell> open_mw_lib gcdGCDUnit_rtl_LIB icc_shell> import_designs "../../dc-syn/current-dc/results/gcdGCDUnit_rtl.mapped.ddc" \ -format "ddc" -top "gcdGCDUnit_rtl" -cel "gcdGCDUnit_rtl" icc_shell> set_tlu_plus_files \ -max_tluplus "$stdcells_home/max.tluplus" \ -min_tluplus "$stdcells_home/min.tluplus" \ -tech2itf_map "$stdcells_home/tech2itf.map"

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icc_shell> derive_pg_connection \ -power_net "VDD" -power_pin "VDD" -ground_net "VSS" -ground_pin "VSS" \ -create_ports "top" # Make an initial floorplan and synthesize power rails. At this point, you # can see the estimated voltage drops on the power rails. # The numbers in the right column of the GUI are specied in mW. icc_shell> create_floorplan \ -control_type "aspect_ratio" -core_aspect_ratio "1" \ -core_utilization "0.7" -row_core_ratio "1" \ -left_io2core "30" -bottom_io2core "30" -right_io2core "30" -top_io2core "30" \ -start_first_row icc_shell> create_fp_placement icc_shell> synthesize_fp_rail \ -power_budget "1000" -voltage_supply "1.2" -target_voltage_drop "250" \ -output_dir "./pna_output" -nets "VDD VSS" -create_virtual_rails "M1" \ -synthesize_power_plan -synthesize_power_pads -use_strap_ends_as_pads # If you have met your power budget, go ahead and commit the power plan. icc_shell> commit_fp_rail # Perform clock tree synthesis. To look at the generated clock tree choose # Clock > Color By Clock Trees. Hit Reload, and then hit OK on the popup window. # Now you will be able to see the synthesized clock tree. icc_shell> clock_opt -only_cts -no_clock_route icc_shell> route_zrt_group -all_clock_nets -reuse_existing_global_route true # Route the remaining nets icc_shell> route_opt -initial_route_only icc_shell> route_opt -skip_initial_route -effort low # Add filler cells. icc_shell> insert_stdcell_filler \ -cell_with_metal "SHFILL1 SHFILL2 SHFILL3" \ -connect_to_power "VDD" -connect_to_ground "VSS" icc_shell> route_opt -incremental -size_only # Your design is now on silicon! Generate the post place and route netlist, # the constraint file, and parasitics files to generate power estimates. icc_shell> icc_shell> icc_shell> icc_shell> icc_shell>

change_names -rules verilog -hierarchy write_verilog "gcdGCDUnit_rtl.output.v" write_sdf "gcdGCDUnit_rtl.output.sdf" write_sdc "gcdGCDUnit_rtl.output.sdc" extract_rc -coupling_cap

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icc_shell> icc_shell> icc_shell> icc_shell> icc_shell>

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write_parasitics -format SBPF -output "gcdGCDUnit_rtl.output.sbpf" source ./find_regs.tcl find_regs gcdTestHarness_rtl/gcd save_mw_cel close_mw_cel

You can now use various commands to analyze the layout, display reports, and further optimize your design. Using the shell directly is useful for finding out more information about a specific command or playing with various options, but for reproducibility and convenience reasons you will primarily use TCL scripts to control this tool. However, due to the visual nature of layout we will likely be using the IC Compiler GUI often to examine our results, so it is recommended you familiarize yourself with this tool. The final step in the Manual Place and Route process is exiting the ICC shell and deleting your build directory: icc_shell-topo> exit % cd $TUTROOT/build/icc-par % rm -rf manual

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Automated IC Compiler Build Process

Typing each command via the shell is a tedious and error-prone process, and should typically be avoided. Instead, we make use of scripts to automate the process of building our tools for us. The landscape of TCL scripts automating our IC Compiler place and route flow is significantly more complicated than that of the Design Compiler synthesis flow used in Tutorial 2. As a result we will refrain from listing the various TCL scripts and Makefiles in the flow, partially for the sake of brevity and partially because the TAs don’t fully understand what everything does yet! Thanks to the configuration information provided by the Makefiles and the TCL scripts, the place and route process can be completely automated. The following commands will automatically place and route your design and save several text reports to the build directory: % cd $TUTROOT/build/icc-par % make You should see IC Compiler start and then execute the commands located in the TCL scripts. The results of place and route are stored in new build directories, just like in the Design Compiler flow. Also like the DC flow each build directory will contain copies of all TCL scripts used to perform each run, this way it’s possible to go back and check the configuration of a specific build. The current-icc symlink will always point to the most recent build directory. Executing make will not re-run place and route unless it detects relevant files have changed. If you wish to force a recompile without doing a make clean, simply remove the current-icc symlink. The following commands will force a resynthesis without actually changing any of the source TCL scripts. % cd $TUTROOT/build/icc-par % rm -f current-icc % make Eventually you will need to modify the build system to synthesize new designs you come up with for the labs. To modify the Makefile so that it will build different sources, you will need to change: • the name of the toplevel Verilog module in your design • the name of the test harness module • the name of the toplevel module instance in your design

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Interpreting the Place and Route Reports

The primary output from the place and route scripts is the layout that you view in the IC Compiler GUI. However, in addition to layout IC Compiler will generate several textual reports that detail various aspects of your placed and routed design. Many of these reports are identical in format to the reports we saw in the Design Compiler tutorial, but many results in the post-place-and-route reports should be more accurate than those in the post-synthesis reports (ie. area and timing). • • • • • • • • •

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reports/chip finish.mapped.area.rpt - Area information for each module instance reports/chip finish.mapped.clock timing.rpt - Clock timing information reports/chip finish.mapped.clock tree.rpt - Clock tree information reports/chip finish.mapped.power.rpt - Power information for each module instance reports/chip finish.mapped.qor.rpt - QoR (Quality of Result) information and statistics reports/chip finish.mapped.reference.rpt - Information on references reports/chip finish.mapped.sum.rpt - Summary of the placed and routed design reports/chip finish.mapped.timing.rpt - Contains critical timing paths log/dc.log - Log file of all output during DC run

Using the IC Compiler GUI to Analyze Place and Route

As you went through the commands described in the Manual IC Compiler Build Process, you should have noticed the design changing in the ICC GUI as various components were added to the chip layout. Typically you will use the automated build process and then use the ICC GUI after the fact to visualize your design, but in this section we want to quickly point out some interesting visualizations that appear when performing the Manual Build process. After creating an initial floorplan and synthesizing power rails using the create fp placement and synthesize fp rail commands, the GUI will display the estimated voltage drops on the power rails (Figure 2). You’ll also notice power numbers in the right hand column of the GUI, which are specified in mW .

Figure 2: Estimated voltage drops shown in IC Compiler

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Once the clock tree is created (using the clock opt and route zrt group commands) you can visualize the generated tree by selecting Clock > Color By Clock Trees from the menu bar. After hitting Reload, and then OK on the popup window, you will be able to see the synthesized clock tree (Figure 3).

Figure 3: Synthesized clock tree shown in IC Compiler After using the route opt commands are executed, you should be able to see the routed signals as demonstrated in Figure 4. If you look at the routing before entering the insert stdcell filler command, you will notice that there are various holes in the placement. These holes are filled up with filler cells which are just empty standard cells that connect the power and ground rails. If you analyze the design you’ll notice the Synopsys 90nm process provides nine metal layers for routing, although Metal 1 is mostly used by the standard cell layout itself.

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Acknowledgements

Many sources have contributed to the content of this tutorial. The original material for this tutorial was developed as a lab for the CS250 VLSI Systems Design course at University of California at Berkeley by Yunsup Lee. Contributors include: Krste Asanovi´c, Christopher Batten, John Lazzaro, and John Wawrzynek. Versions of that lab have been used in the following courses: • CS250 VLSI Systems Design (2009-2011) - University of California at Berkeley • CSE291 Manycore System Design (2009) - University of California at San Diego

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Figure 4: Routed signals shown in IC Compiler

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