Quiz 2014, questions and answers PDF

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Summary

Quiz CompilationProblem 1: Design a 4-bit combinational circuit 2’s complementer. (a) Show the truth table (inputs should be shown in ascending order) of the above circuit Input Minterm Output A B C D m W X Y Z 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 2 1 1 1 0 0 0 1 1 3 1 1 0 1 0 1 0 0 4 1 1 0 0...

Description

Quiz Compilation Problem 1: Design a 4-bit combinational circuit 2’s complementer. (a) Show the truth table (inputs should be shown in ascending order) of the above circuit Input

Minterm

Output

A

B

C

D

m

W

X Y

Z

0

0

0

0

0

0

0 0

0

0

0

0

1

1

1

1 1

1

0

0

1

0

2

1

1 1

0

0

0

1

1

3

1

1 0

1

0

1

0

0

4

1

1 0

0

0

1

0

1

5

1

0 1

1

0

1

1

0

6

1

0 1

0

0

1

1

1

7

1

0 0

1

1

0

0

0

8

1

0 0

0

1

0

0

1

9

0

1 1

1

1

0

1

0

10

0

1 1

0

1

0

1

1

11

0

1 0

1

1

1

0

0

12

0

1 0

0

1

1

0

1

13

0

0 1

1

1

1

1

0

14

0

0 1

0

1

1

1

1

15

0

0 0

1

(b) Determine the Boolean expression of the outputs signals in SOP form W:

X:

CD AB 00 01 11 10

00

01

11

10

0 1 0 1

1 1 0 0

1 1 0 0

1 1 0 0

CD AB 00 01 11 10

W=AB’C’D’+A’B+A’D+A’C

00

01

11

10

0 1 1 0

1 0 0 1

1 0 0 1

1 0 0 1

X=BC’D’+B’D+B’C

Y:

Z:

CD AB 00 01 11 10

00

01

11

10

0 0 0 0

1 1 1 1

0 0 0 0

1 1 1 1

Y=C’D+CD’

CD AB 00 01 11 10

00

01

11

10

0 0 0 0

1 1 1 1

1 1 1 1

0 0 0 0

Z=D COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 3 COMPILATION PAGE 1

Problem 2: Design a combinational circuit that generates the 10’s complement of a BCD digit (a) Show the truth table (in ascending order) for the above circuit Input

Minterm

Output

A

B

C

D

m

W

X Y

Z

0

0

0

0

0

1

0 1

0

0

0

0

1

1

1

0 0

1

0

0

1

0

2

1

0 0

0

0

0

1

1

3

0

1 1

1

0

1

0

0

4

0

1 1

0

0

1

0

1

5

0

1 0

1

0

1

1

0

6

0

1 0

0

0

1

1

1

7

0

0 1

1

1

0

0

0

8

0

0 1

0

1

0

0

1

9

0

0 0

1

1

0

1

0

10

x

x

x

x

1

0

1

1

11

x

x

x

x

1

1

0

0

12

x

x

x

x

1

1

0

1

13

x

x

x

x

1

1

1

0

14

x

x

x

x

1

1

1

1

15

x

x

x

x

(b) Determine the Boolean expression of the outputs signals in POS form W:

X:

CD 00 01 AB 00 1 1 01 0 0 11 x x 10 0 0 W’=B+A+CD

11

10

0 0 x x

1 0 x x

CD AB 00 01 11 10

00

01

11

10

0 1 x 0

0 1 x 0

1 0 x x

0 1 x x

X’=B’D’+B’C’+BCD

W = A’B’ (C’+D’)

X = (B+D) (B+C) (B’+C’+D’)

Y:

Z:

CD 00 01 AB 00 1 0 01 1 0 11 x x 10 1 0 Y’=C’D+CD’ Y = (C+D’) (C’+D)

11

10

1 1 x x

0 0 x x

CD AB 00 01 11 10

00

01

11

10

0 0 x 0

1 1 x 1

1 1 x x

0 0 x x

Z’=D’ Z=D

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 3 COMPILATION PAGE 2

Problem 3: Design an excess-3-to-BCD Code Converter, requiring that all invalid input combinations give 1111 as the output code. Show clearly the following: (a) Truth table (ascending order) Input

Minterm

Output

A

B

C

D

m

W

X Y

Z

0

0

0

0

0

1

1 1

1

0

0

0

1

1

1

1 1

1

0

0

1

0

2

1

1 1

1

0

0

1

1

3

0

0 0

0

0

1

0

0

4

0

0 0

1

0

1

0

1

5

0

0 1

0

0

1

1

0

6

0

0 1

1

0

1

1

1

7

0

1 0

0

1

0

0

0

8

0

1 0

1

1

0

0

1

9

0

1 1

0

1

0

1

0

10

0

1 1

1

1

0

1

1

11

1

0 0

0

1

1

0

0

12

1

0 0

1

1

1

0

1

13

1

1 1

1

1

1

1

0

14

1

1 1

1

1

1

1

1

15

1

1 1

1

(b) Determine the Boolean Expression for the output signals in POS form W:

X:

CD 00 01 11 10 AB 00 1 1 0 1 01 0 0 0 0 11 1 1 1 1 10 0 0 1 0 W’=A’B+A’CD+AB’C’+AB’D’

CD AB 00 01 11 10

01

11

10

1 0 0 1

1 0 1 1

0 1 1 0

1 0 1 1

X’=A’BD’+A’BC’+BC’D’+B’CD

W = (A+B’) (A+C’+D’) (A’+B+C) (A’+B+D) Y:

00

X = (A+B’+D) (A+B’+C) (B’+C+D) (B+C’+D’) Z:

CD 00 01 11 10 AB 00 1 1 0 1 01 0 1 0 1 11 0 1 1 1 10 0 1 0 1 Y’=BC’D’+AC’D’+A’CD+B’CD Y = (B’+C+D) (A’+C+D) (A+C’+D’) (B+C’+D’)

CD AB 00 01 11 10

00

01

11

10

1 1 1 1

1 0 1 0

0 0 1 0

1 1 1 1

Z’=AB’D+A’BD+A’CD Z = (A’+B+D’) (A+B’+D’) (A+C’+D’)

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 3 COMPILATION PAGE 3

Problem 4: Design a combinational circuit that can detect an error in the representation of a decimal digit in BCD. In other words, the circuit’s output is equal to 1 when the input ABCD contains any one of the six unused bit combinations in the BCD code. Show clearly the following: (a) The Circuit’s Truth Table Input

Minterm

Output

A

B

C

D

m

F

0

0

0

0

0

0

0

0

0

1

1

0

0

0

1

0

2

0

0

0

1

1

3

0

0

1

0

0

4

0

0

1

0

1

5

0

0

1

1

0

6

0

0

1

1

1

7

0

1

0

0

0

8

0

1

0

0

1

9

0

1

0

1

0

10

1

1

0

1

1

11

1

1

1

0

0

12

1

1

1

0

1

13

1

1

1

1

0

14

1

1

1

1

1

15

1

(b) Map with most economical grouping of minterms F: CD AB 00 01 11 10

00

01

11

10

0 0 1 0

0 0 1 0

0 0 1 1

0 0 1 1

(c) The expression of the output signal F(A,B,C,D) in SOP Form. F = AB + AC

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 3 COMPILATION PAGE 4

Problem 5: Design a combinational circuit with three inputs (XYZ) and one output (F). The output signal is 1 when the decimal value of the inputs is an odd number. Show clearly the following: (a) The Circuit’s Truth Table Excess-3 Code

Minterm Output

A

B

C

m

F

0

0

0

0

0

0

0

1

1

1

0

1

0

2

0

0

1

1

3

1

1

0

0

4

0

1

0

1

5

1

1

1

0

6

0

1

1

1

7

1

(b) Map with most economical grouping of minterms F: CD A 00 01

00

01

11

10

0 0

1 1

1 1

0 0

(c) The expression of the output signal F(X,Y,Z) in SOP Form. F=Z

COE117 LOGIC CIRCUITS AND THEORY QUIZ NO. 3 COMPILATION PAGE 5

Problem 6: design a combinational circuit that accepts a 4-bit number (ABCD) and generates a 3-bit binary number output (XYZ) that approximates the square root of the number. If the square root is 3.5 or larger, give a result of 4. If the square root is...