Single Stuck-at Fault - Prof. Reddy PDF

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Unit I: Introduction to Testing & Verification

2020

Single Stuck-at Fault We assume that the circuit is modeled as an interconnection (called a netlist) of Boolean gates.

A stuck-at fault is assumed to affect only the

interconnection between gates. Each connecting line can have two types of faults: stuck-at -1 and stuck-at-0 (commonly written as s-a-1 and s-a-0). Thus, a line with a stuck-at-1 fault will always have a logic state 1 irrespective of the correct logic output of the gate driving it. In general, several stuck-at faults can be simultaneously present in the circuit. A circuit with n lines can have possible 3^(n) – 1 stuck line combinations. This is because each line can be in one of the three states: s-a-1, s-a-0, or faultfree. All combinations except one having all lines in fault-free states are counted as faults. Clearly, even a moderate value of n will give an enormously large number of multiple stuck-at faults. It is a common practice, therefore, to model only single stuck-at faults. An nline circuit can have at most 2n single stuck-at faults.

Three properties (or assumptions) characterize a single stuck-at fault: 1. Only one line is faulty. 2. The faulty line is permanently set to either 0 or 1. 3. The fault can be at an input or output of a gate.

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Unit I: Introduction to Testing & Verification

2020

A stuck-at -1 fault as marked at the output of the OR gate means that the faulty signal remains 1 irrespective of the input state of the OR gate. A 00 input to the OR gate will produce a 0 output in the normal circuit. The faulty circuit will have a 1 there. This signal state must be propagated to the output of the AND2 gate, which is an observable output of this circuit. This is done by setting the other input of AND2 as 1, which is justified by setting the inputs of AND1 as 11. Now we have the input vector 1100 as a test for the s-a-1 fault since for this vector the normal output (true response) and the faulty output differ. Figure has seven lines, which are the potential sites for single stuck-at faults. The number of possible faults is 14. As shown, the single fault h s-a-0 is detectable by a 10 input. Signal lines g, h, and i, commonly known as a signal net, carry the same signal value. The 10 input also activates single s-a-0 faults on g and i. But, only g s-a-0 is detectable by this input.

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Unit I: Introduction to Testing & Verification

2020

The effect of fault i s-a-0 is blocked from propagating to the primary output z by f = 0 which uniquely sets k =1. We notice that the faults on the fanout branches of a net are not identical. In a logic circuit, a net contains a stem or source (g in this circuit) and fanout branches (h and i.)

The stem is the output of some gate and fanout branches are inputs of some other gates. To consider all possible faults, we model single stuck-at faults on the stem and all fanout branches of the net. Considering all nets in the circuit, this is equivalent to modeling faults on inputs and outputs of all gates

Figure has 12 fault sites and hence we would model 24 single stuck-at faults in this circuit. To reduce this number, we will use the concepts of fault equivalence and fault dominance.

Fault Equivalence Let us consider a single-output combinational circuit with n input variables. We will denote its output function as f0(V) where V is an n-bit Boolean vector. To consider two faults, designated as fault 1 and fault 2, let the output function in the presence of fault 1 be f1(V) and that in the presence of fault 2 be f 2(V). Any test V for fault 1 must produce different values for f0(V) and f1(V). This condition can be expressed as: f0(V) xor f1(V) = 1 ----- equ 1 3 Department of Electronics & Communication Engineering

Unit I: Introduction to Testing & Verification

2020

Similarly, a test for fault 2 must satisfy f0(V) xor f2(V) = 1 ----- equ 2 When fault 1 and fault 2 have exactly the same tests, i.e., all vectors that satisfy Equation 1 also satisfy Equation 2, and vice-versa, then the Boolean functions on the left hand sides of the two equations are identical. That is, [f0(V) xor f1(V)] xor [f0(V) xor f2(V)] = 0 ------- equ 3 The equation is further rewritten as – f1(V) xor f2(V) = 0 -------- equ 4 Equation 4, known as the indistinguishability condition, shows that the two faulty functions are identical when the faults have the same set of tests.

Fault Equivalence: Two faults of a Boolean circuit are called equivalent if they transform the circuit such that the two faulty circuits have identical output functions. Equivalent faults are also called indistinguishable and have exactly the same set of tests.

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