Software Lab 2 Report PDF

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Software Lab 2 report for CSE 2300w/2301...

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Binary to Ternary Numerals Introductions: In this lab, we are required to design a circuit that converts a 4-digit Binary into Ternary XYZ. Binaries are labeled from 00002 to 10102, and the possible outcomes are 0003 to 1013. The calculation involves translation and conversion between Binary and Ternary, for example, 10102 = 1013 = 10 in decimal. Though X, Y and Z are represented in Binary, they will be transferred into Ternary and inputted into corresponding position with Ternary number. For example, 0001 in Z means a 001 in XYZ, and 0010 in Binary Z means 002 in Ternary in XYZ. At the same time, the Hex number represents as a counter for Ternary, since the Objective only required for number Z, Hex also represents the number of Binary Z in Ternary as well. Results Firstly, we need to find out the Equation of Z number. The Equation of Zs are: Z3 and Z2 is always 0. When Z1 = 1, the Binaries are: 0010, 0101, 1000, 1011 and 1110 which means the Equation should be: D’CB’A + DC’B’A + D’C’BA’ + DC’BA + DCBA’ When Z0 = 1, the Binaries are: 0001, 0100, 0111, 1010 and 1101, which means the Equation should be: D’C’B’A + D’CB’A + D’CBA + DC’BA’ + DCB’A

Below is a re-organized Equation table for each Z-number:

Z3 0 Z2 0 Z1 D’CB’A + DC’B’A + D’C’BA’ + DC’BA + DCBA’ Z0 D’C’B’A + D’CB’A + D’CBA + DC’BA’ + DCB’A According to the Form and the result, we can map and test the circuit. Since the objective is stated, we only need to map a circuit that works for Z. Below is the truth table I created according to the circuit results Decimal 0

DCBA(Binary) 0000

Z(Binary) 0000

H(Hex) 0

1 2 3 4 5

0001 0010 0011 0100 0101

0001 0010 0000 0001 0010

1 2 0 1 2

6 7 8 9 10 11 12 13 14 15

0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

0000 0001 0010 0000 0001 0010 0000 0001 0010 0000

0 1 2 0 1 2 0 1 2 0

The complete circuit is shown above, to be noticed that Z2 and Z3 are constant 0 on the right upper corner and should not be changed according to the instruction. The grey lines in the middle does not exist, since it’s a line divided the page in the PDF printed version of the circuit. Discussion: While mapping the Circuit, I first tries to just simply connects the signals, however, I soon

discovered that the signal is to crowded and becomes a complete complex of chaos, so I decided to completely delete all wires and re-route all circuit along with signals. Finding that there are basically 8 results, I decided to separate then into 8 different surfaces as shown in the circuit figure above, from DCBA to D’C’B’A’. Since I’ve mapped 2 AND gates as a pair, the first input should always connect to D-lines, whether it’s D or D’, while the last/forth one will always connect to A-lines. This way, not only the entire circuit becomes neater, it’s also very friendly for debugging. In case I mess up, I marked each line with what they are, as shown above, so it will be more helpful for debugging in the future. Questions: The best way for me to reduce the number of gates currently, is to use 3 or 4 or multiple-input AND/OR gates in this scenario. The current layout should already be the optimal solution to satisfy the requirement, but without multiple-input gates allowed, the process of combining (AND) and selecting (OR) require s this much gates for the circuit to operate....