Ultra 96-V2 Rev1 Schematic PDF

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Download Ultra 96-V2 Rev1 Schematic PDF

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Ultra96 SBC V2 Avnet Engineering Services www.avnet.me/ultra96-v2

Sheet Name 01 - Avnet Lead Sheet A

A

02 - Block Diagram 03 - Bank 500, Bank 501, Bank 502, Bank 503 04 - Bank 504, Bank 505 05 - SD Card, RADIO 06 - USB 3.0 MicroAB 07 - USB2.0 Downstream Device & Clock Gen 08 - Bank 0, Bank 26, Bank 65, Bank 66 09 - Switches, LEDs, JTAG 10 - Bank Power and Decoupling 11 - LPDDR4 Device 12 - USB 3.0 Dual Port Hub 13 - Jx_Jy Expansion Headers, Power On

B

Ultra96 SBC V2

14 - Display Port 15 - Rocky PMIC #1 16 - Rocky PMIC #2

B

(AES-ULTRA96-V2-G)

17 - Manhattan PMIC #3 18 - Back Page

Revision

C

C

https://www.96boards.org/products/ce/

Copyright 2019, Avnet, Inc. All Rights Reserved. This material may not be reproduced, distributed, republished, displayed, posted, transmitted or copied in any form or by any means without the prior written permission of Avnet, Inc. AVNET and the AVNET logo are registered trademarks of Avnet, Inc. All trademarks and trade names are the properties of their respective owners and Avnet, Inc. disclaims any proprietary interest or right in trademarks, service marks and trade names other than its own. D

D

Avnet is not responsible for typographical or other errors or omissions or for direct, indirect, incidental or consequential damages related to this material or resulting from its use. Avnet makes no warranty or representation respecting this material, which is provided on an "AS IS" basis. AVNET HEREBY DISCLAIMS ALL WARRANTIES OR LIABILITY OF ANY KIND WITH RESPECT THERETO, INCLUDING, WITHOUT LIMITATION, REPRESENTATIONS REGARDING ACCURACY AND COMPLETENESS, ALL IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY, SUITABILITY OR FITNESS FOR A PARTICULAR PURPOSE, TITLE AND/OR NON-INFRINGEMENT. This material is not designed, intended or authorized for use in medical, life support, life sustaining or nuclear applications or applications in which the failure of the product could result in personal injury, death or property damage. Any party using or selling products for use in any such applications do so at their sole risk and agree that Avnet is not liable, in whole or in part, for any claim or damage arising from such use, and agree to fully indemnify, defend and hold harmless Avnet from and against any and all claims, damages, loss, cost, expense or liability arising out of or in connection with the use or performance of products in such applications. Note1 1

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Avnet Engineering Services Project Name:

Ultra96 SBC V2 SCH-US1SBC

Doc Num:

PCB Rev: BOM: Date:

1

3/1/2019

Sheet Title:

Size:

01 - Avnet Lead Sheet.SchDoc

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C

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Avnet Engineering Services Project Name:

Ultra96 SBC V2 Doc Num: SCH-US1SBC

PCB Rev: BOM: Date:

1

3/1/2019

Sheet Title:

Size:

02 - Block Diagram.SchDoc

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BANK 500, BANK 501, BANK 502, BANK 503 U1E A

BANK 502

BANK 501

BANK 500

U1F

BANK 500

U1G

BANK 501 Y6 AB6 AB5 AA6 W6 AB4 AA4 Y5 AA3 Y3 Y4 W5 W3 AB2 W2 AA2 V5 V3 V4 Y1 AA1 U6 U5 V2 W1 U4

B

R1 R2

R3 R4 R5 R6

30.1 30.1

30.1 30.1 30.1 30.1

MIO1_UART1_RX MIO0_UART1_TX

MIO25_VBUS_DET MIO24_SD0_DETECT MIO23_GPIO_PB MIO22_SD0_CLK MIO21_SD0_CMD MIO20_PS_LED0 MIO19_PS_LED1 MIO18_PS_LED2 MIO17_PS_LED3 MIO16_SD0_DAT3 MIO15_SD0_DAT2 MIO14_SD0_DAT1 MIO13_SD0_DAT0 MIO12_I2C_MUX_RESET_N MIO11_SPI1_MOSI MIO10_SPI1_MISO MIO9_SPI1_CS MIO8_RADIO_EN MIO7_RAD_RST_N MIO6_SPI1_SCLK MIO5_I2C1_SDA MIO4_I2C1_SCL MIO3_UART0_TX_BT_HCI_RX MIO2_UART0_RX_BT_HCI_TX

12[1D], 7[3B] 5[3D] 9[1A] 5[2D] 5[2D] 9[3B] 9[4B] 9[3C] 9[4C] 5[2C] 5[2C] 5[2C] 5[2C] 13[4D] 13[1A] 13[1A] 13[1A] 5[2A] 8[3D] 13[1A] 13[4C] 13[4C] 5[2A] 5[2A]

C13 A13 D13 A12 B12 C12 A11 B11 E13 D12 B10 D11 C10 C9 E11 D10 E10 F13 E9 F12 F11 G10 F9 G12 G11 G9

BANK 502

MIO35

NT11

MIO33 MIO32

NT12 NT13

R7

XCZU3EG-1SBVA484I

XCZU3EG-1SBVA484I

MIO51_SD1_CLK MIO50_SD1_CMD MIO49_SD1_D3 MIO48_SD1_D2 MIO47_SD1_D1 MIO46_SD1_D0 MIO45_PS_GPIO1_5 MIO44_PS_GPIO1_4 MIO43_SPI0_MOSI MIO42_SPI0_MISO MIO41_SPI0_CS MIO40_PS_GPIO1_3 MIO39_PS_GPIO1_2 MIO38_SPI0_SCLK MIO37_PS_GPIO1_1 MIO36_PS_GPIO1_0 TP1 MIO34_POWER_KILL_N TP2 TP3 MIO31_MHTN_ALRT MIO30_DP_AUX_IN MIO29_DP_OE MIO28_DP_HPD MIO27_DP_AUX_OUT MIO26_PWR_INT

4.75K

A

B18 F18 B17 D18 D17 C17 F17 A17 A16 B16 G17 D16 B15 E16 F16 C15 G16 D15 E15 A14 B14 E14 C14 G15 F14 G14

5[2B] 5[2B] 5[2B] 5[2B] 5[2B] 5[2B] 13[5B] 13[4B] 13[5A] 13[5A] 13[5A] 13[5B] 13[4B] 13[5A] 13[5B] 13[4B] 13[4C] 17[2C] 14[1C] 14[1C] 14[1C] 14[1B] 13[6C]

MIO77_PWR_ALERT_N MIO76_WLAN_IRQ MIO75_USB1_DATA7 MIO74_USB1_DATA6 MIO73_USB1_DATA5 MIO72_USB1_DATA4 MIO71_USB1_DATA3 MIO70_USB1_STP MIO69_USB1_DATA1 MIO68_USB1_DATA0 MIO67_USB1_NXT MIO66_USB1_DATA2 MIO65_USB1_DIR MIO64_USB1_CLK MIO63_USB0_DATA7 MIO62_USB0_DATA6 MIO61_USB0_DATA5 MIO60_USB0_DATA4 MIO59_USB0_DATA3 MIO58_USB0_STP MIO57_USB0_DATA1 MIO56_USB0_DATA0 MIO55_USB0_NXT MIO54_USB0_DATA2 MIO53_USB0_DIR MIO52_USB0_CLK

15[2C], 16[1C], 17[2C] 5[4A] 7[1B] 7[1B] 7[1B] 7[1B] 7[1B] 7[2B] 7[1B] 7[1B] 7[2B] 7[1B] 7[2B] 7[2B] 6[1B] 6[1B] 6[1B] 6[1B] 6[1B] 6[3B] 6[1B] 6[1B] 6[3B] 6[1B] 6[3B] 6[3B]

B

XCZU3EG-1SBVA484I

+VCC_PSAUX

OFF BOARD UART & XNSLTR +VCC_PSAUX +3.3V

2

MIO1_UART1_RX

(Refer to User's Guide for information)

J1 1 2 3 4

D

S

BSS138-7-F R10 0

DNP

C

BOARD ID STRAPPING OPTIONS

4 PIN HDR

R9 10.00K

Q1 3

G

1

R8 10.00K

GND

MMT-104-01-T-SH-LC 0 JT1 1 +3.3V

BANK 503 U1H

MIO35

L12 K16 K18 K15 H13 H12 J13 J12 J16 H15 J15 H18 H17 J17 K12 K14 H14 K13

R11 R12 10.00K

+VCC_PSAUX

3 Default: Pin 1-2: 0 ohm

3

Q2

2

G

1

10.00K MIO0_UART1_TX

+VCC_PSAUX JT8 3

2

+VCC_PSAUX JT9 3

2

MIO33

MIO32

2

BANK 503

2

+VCC_PSAUX +3.3V

+VCC_PSAUX JT7 3

D

S

BSS138-7-F R14 0

DNP

PS_ERR_OUT PS_ERR_STAT

NT10

PS_MODE3 PS_PAD_IN PS_PAD_OUT

PS_DONE

9[5B]

PS_INIT_N JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS PS_MODE0 PS_MODE1 PS_MODE2

9[5B] 9[2A] 9[2B] 9[2B] 9[2A] 9[1C] 6[1D] 9[1C]

POWER_GOOD

13[5A], 15[2C], 16[1C], 17[2B], 6[1D], 9[1B]

PS_REF_CLK PS_SRST_N

7[5B] 9[2B]

1

TP4

1

1 C

TP5

10K (1-2)

10K (1-2)

GND

GND

10K (1-2)

GND

32KHz RTC XTAL X1 PS_PAD_IN

PS_PROG_N

C1 27pF

2

1

PS_PAD_OUT

32.768kHz R13

C2 27pF

4.7M

XCZU3EG-1SBVA484I PS_MODE3

R15

GND

4.75K

GND

GND +VCC_PSAUX

D

R16

4.75K

PS_PROG_N

D

Avnet Engineering Services Project Name:

Ultra96 SBC V2 Doc Num: SCH-US1SBC

PCB Rev: BOM: Date:

1

3/1/2019

Sheet Title:

01

Time:

Size:

Sheet:

03 - Bank 500, Bank 501, Bank 502, Bank 503.SchDoc B

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BANK 504, BANK 505

A

A

BANK 504 - DDR

BANK 504 - DDR

U1I PS_DDR_CAA0 PS_DDR_CAA1 PS_DDR_CAB0 PS_DDR_CAB1 PS_DDR_CAB2 PS_DDR_CAB3 PS_DDR_CAB4 PS_DDR_CAB5

11[2B] 11[2B] 11[2B] 11[2B]

PS_DDR_CAA2 PS_DDR_CAA3 PS_DDR_CAA4 PS_DDR_CAA5

B

11[2B] 11[2C] 11[2B], 11[2C] 11[5C] 11[2B] 11[2B] 11[2B], 11[2C] 11[5C] 11[2B] 11[2B] 11[2C] 11[2C]

C

11[5A] 11[5B] 11[5B] 11[5B] 11[5B]

PS_DDR_CKA_T PS_DDR_CKB_T PS_DDR_CKE0 PS_DDR_CKE1 PS_DDR_CKA_C PS_DDR_CKB_C PS_DDR_CS0_N PS_DDR_CS1_N PS_DDR_DMA0 PS_DDR_DMA1 PS_DDR_DMB0 PS_DDR_DMB1 PS_DDR_DQ0 PS_DDR_DQ1 PS_DDR_DQ10 PS_DDR_DQ11 PS_DDR_DQ12

U1K

BANK 504

BANK 504 11[2B] 11[2B] 11[2B] 11[2B] 11[2B] 11[2B] 11[2B] 11[2B]

BANK 505 - GTR

U1J

AA22 AB20 Y21 AA21 AA18 AA19 AA17 AA16 Y16 W16 AB17 AB19 AB21 AB16 Y20 Y19 W17 Y18 U15 T21 U17 V17 U16 W18 V20 V18 U22 U21 W20 V19 V22 U20 AB9 AB14 U9 W13 R19 AB11 Y10 AA12 AB12 Y14

11[5B] 11[5B] 11[5B] 11[5A] 11[5B] 11[5B] 11[5B] 11[5B] 11[5B] 11[5B] 11[5B] 11[5C] 11[5C] 11[5C] 11[5B] 11[5B] 11[5B] 11[5B] 11[5B] 11[5B] 11[5B] 11[5B] 11[5B] 11[5B]

XCZU3EG-1SBVA484I

PS_DDR_DQ13 PS_DDR_DQ14 PS_DDR_DQ15 PS_DDR_DQ16 PS_DDR_DQ17 PS_DDR_DQ18 PS_DDR_DQ19 PS_DDR_DQ2 PS_DDR_DQ20 PS_DDR_DQ21 PS_DDR_DQ22 PS_DDR_DQ23 PS_DDR_DQ24 PS_DDR_DQ25 PS_DDR_DQ26 PS_DDR_DQ27 PS_DDR_DQ28 PS_DDR_DQ29 PS_DDR_DQ3 PS_DDR_DQ30 PS_DDR_DQ31 PS_DDR_DQ4 PS_DDR_DQ5 PS_DDR_DQ6

11[5B]

PS_DDR_DQ7

11[5C] 11[5C] 11[5C] 11[5C] 11[5C] 11[5C]

PS_DDR_DQ8 PS_DDR_DQ9 PS_DDR_DQSA0_C PS_DDR_DQSA1_C PS_DDR_DQSB0_C PS_DDR_DQSB1_C

11[5C] 11[5C] 11[5C] 11[5C]

PS_DDR_DQSA0_T PS_DDR_DQSA1_T PS_DDR_DQSB0_T PS_DDR_DQSB1_T

11[2D] PS_DDR_RST_N

BANK 505

AA14 Y15 AB15 W8 W7 V7 V10 AB10 U7 T9 U10 T10 U11 U12 W12 W11 V14 U14 W10 W15 V15 AA8 Y8 AB7 T22 P22 R21 P21 R18 P18 AA7 N18 N19 AA11 Y11 AA9 AA13 V8 V13 R20 Y9 Y13 V9 V12 P20 W22 W21 U19 T18 T19 R23 240

6[4B] GTR_LANE2_RX_N 12[1B] GTR_LANE3_RX_N 6[4B] 12[1B] 14[4B] 14[4B] 6[4B] 12[1B] 14[4B] 14[4B] 6[4B] 12[1B] 7[5B] 7[5B] 7[5B] 7[5B]

GTR_LANE2_RX_P GTR_LANE3_RX_P GTR_LANE0_TX_N GTR_LANE1_TX_N GTR_LANE2_TX_N GTR_LANE3_TX_N GTR_LANE0_TX_P GTR_LANE1_TX_P GTR_LANE2_TX_P GTR_LANE3_TX_P GTR_CLK0_USB_26M_N GTR_CLK0_USB_26M_P GTR_CLK1_DP_27M_N GTR_CLK1_DP_27M_P

C10 C12

0.1uF C11 0.1uF 0.1uF C13 0.1uF

U26M_N U26M_P U27M_N U27M_P

LAYOUT NOTE: Pair differential routing to appropriate name.

M22 H22 D22 B22 M21 H21 D21 B21 K22 F22 C20 A20 K21 F21 C19 A19 L20 L19 J20 J19 G20 G19 E20 E19 M20

B

XCZU3EG-1SBVA484I R22 500, 0.1%

LAYOUT NOTE: Place 500 ohm resistor close to SoC.

GND

C

XCZU3EG-1SBVA484I LAYOUT NOTE: Place ZQ resistor close to SoC.

GND

D

D

Avnet Engineering Services Project Name:

Ultra96 SBC V2 Doc Num: SCH-US1SBC

PCB Rev: BOM: Date:

1

3/1/2019

Sheet Title:

Size:

04 - Bank 504, BANK 505.SchDoc

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SD CARD, ATWILC3000 WiFi & BT RADIO RADIO: BLUETOOTH, WiFi (SDIO Mode) A

R17

GND 8[3D] 3[2B]

+VCC_PSAUX

1M

MIO7_RADIO_RST_N MIO8_RADIO_EN

GND

U2

+3.3V

12 18 TP6 TP7 TP8 TP9

RADIO_CLK

3[2B] 3[2B] 8[3A] 8[3A]

MIO2_UART0_RX_BT_HCI_TX MIO3_UART0_TX_BT_HCI_RX BT_HCI_RTS BT_HCI_CTS

3[4A] 3[4A] 3[4A] 3[4A] 3[4A] 3[4A]

MIO51_SD1_CLK MIO50_SD1_CMD MIO46_SD1_D0 MIO47_SD1_D1 MIO48_SD1_D2 MIO49_SD1_D3

B

R18 0

+VCC_PSAUX Y1 4

VDD

OUT

DNC

GND

1

R19

0

MIO76_WLAN_IRQ

34 14 15 29 30 31 32 35 16 17

3 4 5 6

RADIO RTC 32.768KHz CLOCK

GND

33

7 19 20 8 9 10 11 2 22 23 24 25 26 27

A

C3 0.1uF C5 10uF

C4 1uF

3[6A]

TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19

1 13 21 28 36 EP

NC NC NC NC

RADIO_CLK

B

C6 0.1uF

3

ATWILC3000-MR110CA

2 GND

GND

32.768kHz DSC6083CI2A-032K768 GND

LAYOUT NOTE: PCB Cutout or no plane routes under antenna area required! See Datasheet.

GND

uSD CARD INTERFACE +VCC_PSAUX +3.3V GND C

17

5

U3

C8 0.1uF

21

C7 0.1uF

GND C

3[2A]

MIO24_SD0_DETECT

25

GND

SEL_B0#

D

GND

24

DAT0_b0 DAT1_b0

CMDa CLKa

GND

MIO21_SD0_CMD MIO22_SD0_CLK

CLK_b0

11

4 9

GND DAT2_b0 DAT3_b0 CMD_b0

DAT0a DAT1a DAT2a DAT3a

T-PAD

3[2A] 3[2A]

6 7 1 3

MIO13_SD0_DAT0 MIO14_SD0_DAT1 MIO15_SD0_DAT2 MIO16_SD0_DAT3

2

3[2B] 3[2B] 3[2A] 3[2A]

Vcc_b1

Vcca

Vcc_b0

+3.3V

DAT0_b1 DAT1_b1 DAT2_b1 DAT3_b1 CMD_b1 CLK_b1

23 22 20

R21

J2

C9 0.1uF

4.75K

2

9

19

3

10

18 16

4

R192

GND

1 +VCC_PSAUX

4.99K

5 14 15 8 10 12 13

11 12 13 14 15 16 6

7 8

R20

240

GND FB1

2201778-1

TXS02612RTWR

GND SH_GND2

D

Avnet Engineering Services Project Name:

GND

Ultra96 SBC V2 Doc Num: SCH-US1SBC

PCB Rev: BOM: Date:

1

3/1/2019

Sheet Title:

Size:

B

05 - SD Card, RADIO.SchDoc

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USB 3.0 MicroAB UPSTREAM INTERFACE A

A

USB 2.0 XNCVR

+VCC_PSAUX

+USB_VB

+5.0V C176 0.1uF

3[6B] 3[6B] 3[6B] 3[6B] 3[6B] 3[6B] 3[6B] 3[6B]

B

8 11 14

+USB_VB

220 Ohm @ 100MHz C178 0.1uF

220 Ohm @ 100MHz

GND

J7

VBAT

32

21

28 30

D0 D1 D2 D3 D4 D5 D6 D7

PWR1 i

FB6

C177 5.6uF FB7

USB3320C-EZK

CPEN

22 19 18 23

C180 2.2uF

PGND

GND 4[5B] GTR_LANE2_TX_N

17 29 2 31 1

MIO58_USB0_STP MIO55_USB0_NXT MIO53_USB0_DIR MIO52_USB0_CLK

3[6B] 3[6B] 3[6B] 3[6B]

GTR_LANE2_TX_N GTR_LANE2_TX_P

C181 USB3_TX2_N 0.1uF C182 USB3_TX2_P 0.1uF

27

REFCLK

RESET

NC

RBIAS

12

33

SPK_L SPK_R

PAD

XO

15 16

26

USB_CLKA

USB_CLKA

5 6 7

GND 4[5A] GTR_LANE2_RX_N 4[5B] GTR_LANE2_RX_P

USB_RST_N

1 2 3 4

ULPI0_D_N ULPI0_D_P USB_ID_3V3

4[5B] GTR_LANE2_TX_P STP NXT DIR CLKOUT

PGND ULPI0_D_N ULPI0_D_P

GND

R151 10.00K

VBUS DM DP ID

REFSEL0 REFSEL1 REFSEL2

3 4 5 6 7 9 10 13

MIO56_USB0_DATA0 MIO57_USB0_DATA1 MIO54_USB0_DATA2 MIO59_USB0_DATA3 MIO60_USB0_DATA4 MIO61_USB0_DATA5 MIO62_USB0_DATA6 MIO63_USB0_DATA7

VDDIO

C179 0.1uF

GND

VDD18 VDD18

VDD33

+VCC_PSAUX

GND

C175 0.1uF

C174 0.1uF

C173 0.1uF

8

GTR_LANE2_RX_N

9

GTR_LANE2_RX_P

10

USB5V0 DD+ ID GND MicA_SSTX-

GND_DRAIN MicA_SSRXMicA_SSRX+ S1 S2 S3 S4

7[5B]

25 D16 PUSB3F96X

R152

USB3_TX2_N

1

CH1

2

4

CH2

CH3

5

C183 0.1uF

CH4 GND

GND

GND

C

USB3_TX2_P GTR_LANE2_RX_N GTR_LANE2_RX_P

GND 3,8

C184 0.1uF

C185 0.1uF

GND

DNP

U15 5 VCC

13[5A], 15[2C], 16[1C], 17[2B], 3[4D], 9[1B] 3[4C]

1

POWER_GOOD

2

PS_MODE1

USB_CLKA

A

4

Y

0

USB_RST_N

USB_RST_N

DNP

12[4B], 7[1B]

B SN74LVC1G08DBVT 3 GND

GND

Layout Notes: 1) USB 2.0 ULPI_D_P/N signals differentially routed @ 90 ohms. 2) USB 3.0 SSTX/RX_P/N routed @ 85 ohms differential. 3) ULPI_VBUS >30 mil thick trace for current.

C

GND Y2

4 3 2

R154

SH_GND5

GND

+VCC_PSAUX +VCC_PSAUX

S1 S2 S3 S4

KMMX-AB10-SMT1SB30TR

24 R153 8.06K

B

MicA_SSTX+

0

U14

20

USB_ID_3V3

USB 3.0 Micro A/B

1

...