Unit 5 - Processor organization: General register organization stack organization. PDF

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Processor organization: General register organization

stack organization. IBM PC
architecture: Motherboard

display adapters

add-on cards

power supply.

Architectural overview of Pentium, P-II, P-III and P-...

Description

UNIT V PROCESSOR ORGANIZATION General register organization: The set of registers in a computer are connected to the ALU using buses and multiplexers. A 14-bit control word specifies two source registers (SELA & SELB), a destination register (SELD), and an operation (OPR). The remaining four bits of the control word can be used to specify the following ALU operations: The registers can be specified using three bits each as follows: Binary SELA SELB SELD Code 000 Input Input None 001

R1

R1

R1

010

R2

R2

R2

011 100

R3 R4

R3 R4

R3 R4

101 110

R5 R6

R5 R6

R5 R6

111

R7

R7

R7

OPR Operation Select 00000 Transfer A

Symbol TSFA

00001 Increment A

INCA

00010 Add A + B

ADD

00101 Subtract A - B SUB 00110 Decrement A

DECA

01000 AND A and B AND 01010 OR A and B

OR

01100 XOR A and B XOR 01110 Complement A COMA 10000 Shift right A

SHRA

11000 Shift left A

SHLA

Stack organization: A stack is a storage device that stores information in a last-in, first-out (LIFO) fashion. A stack has two operations: push, which places data onto the stack, and pop, which removed data from the stack. A computer can have a separate memory reserved just for stack operations. However, most utilize main memory for representing stacks. Hence, all assembly programs should allocate memory for a stack. The SP register is initially loaded with the address of the top of the stack. In memory, the stack is actually upside-down, so when something is pushed onto the stack, the stack pointer is decremented. SP...