Unit7 - 8255 - Lecture notes 7 PDF

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EC-3003 :: MICROPROCESSORS AND MICROCONTROLLERS (Credit - 4)

Unit Seven: Interfacing Chips I. 8255 – Programmable Peripheral Interface

Jabir Hussain ([email protected]) School of Electronics Engineering KIIT University

November 15, 2016

1

8255 Architecture and Pin Diagram

Power Supplies

+5V Group A Port A (8)

GND Group A Control

Bidirectional Data Bus Data Bus Buffer

D7 − D0

Group A Port C Upper (4)

8-Bit Internal Data Bus

Group B Port C Lower (4)

RD WR A1 A0

Read Write Control Logic

Group B Control

Group B Port B (8)

RESET

CS

Figure 1: 8255 Architecture

Figure 2: 8255 Pin Diagram 1

I/O PA7 − PA0

I/O PC7 − PC4

I/O PC3 − PC0

I/O PB7 − PB0

1.1 Need for IO ports The 8255A has 24 I/O pins (out of total 40 pins) that can be grouped primarily in two 8-bit parallel ports: A and B, with the remaining eight bits as port C. The eight bits of port C can be used as individual bits or be grouped in two 4-bit ports: CUPPER (CU) and CLOWER (CL ). The functions of these ports are defined by writing a control word in the control register.

1.1

Need for IO ports

The I/O devices can not be directly interfaced with the microprocessors for reasons which are described below: • I/O devices are not usually equipped with tri-stated buffers, so direct interfacing result in bus-contention. • Device selection logic is usually not present in I/O device. • In order to transfer data (asynchronous, interrupt-driven, etc), we need various handshaking signals which are not provided by the I/O device. • The rate at which data transfer between the µP and I/O device is not same. The rough schematic of interfacing an I/O device is shown below

CS Address Bus

µP

Data Bus

I/O Port

Control Signals

2

Data Bus

I/O Device

2

Chip Select Logic and Port Address

In 8255, CS is used to select the chip, i.e., the decoded address is connected to this pin. A0 and A1 are connected to µP address lines A0 and A1 , respectively and are used to internally decode among Port A, Port B, Port C and Control Register as given below: CS A1

A1

Selected

Valid Operation

0

0

0

Port A

Read and Write

0

0

1

Port B

Read and Write

0

1

0

Port C

Read and Write

0

1

1

Control Register

Write

1

X

X

8255 not selected

–

As an example, the port addresses in the figure below are determined by the CS, A0 and A1 lines. A7 A6 A5 CS

A4

A1 A3

8255

A0 A2 A1 A0

CS

Hex Addr.

Port

A7

A6

A5

A4

A3

A2

A1

A0

1

0

0

0

0

0

0

0

= 80H

A

0

1

= 81H

B

1

0

= 82H

C

1

1

= 83H

Control Register

3

3

Control Word D7

D6

D5

D4

D3

D2

D1

D0

Group B Port C (Lower) : PC3 -PC0 1 = Input 0 = Output Port B 1 = Input 0 = Output Mode Selection 1 = Mode 1 0 = Mode 0

Group A Port C (Upper) : PC7 -PC4 1 = Input 0 = Output Port A 1 = Input 0 = Output Mode Selection 00 = Mode 0 01 = Mode 1 1X = Mode 2

1 = I/O Mode 0 = BSR Mode

Figure 3: 8255A Control Word Format

4

4

BSR Mode

The Bit Set/Reset Mode is concerned only with the eight bits of Port C, which can be set or reset by writing an appropriate control word in the control register. The I/O operations of Port A and Port B are not affected by a BSR control word. Control Word

D7

D6

D5

D4

X

X

X

D3

D2

D1

D0 Bit Set/Reset 1 = Set 0 = Reset

DON’T CARE

B2

B1

B0

0

0

0

PC0

0

0

1

PC1

0

1

0

PC2

0

0

1

PC3

1

0

0

PC4

1

0

1

PC5

1

1

0

PC6

1

1

1

PC7

Bit Select Bit Set Reset Flag 0 = Active Figure 4: BSR Control Word Format

5

5

I/O Mode

There are three basic modes of operation that can be selected by the system hardware (using appropriate control word): • Mode 0 – Basic Input/Output • Mode 1 – Strobed Input/Output • Mode 2 – Bi-directional Bus Each mode will be discussed in detail.

5.1

Mode 0: Simple Input or Output

This mode provides simple input and output operations for each of the three ports. No “handshaking” is required, data is simply written to or read from a specified port. The functional definitions are as follows: 1. Two 8-bit ports (A and B), and two 4-bit ports (C U and CL ). 2. Any port can be input or output. 3. Outputs are latched. 4. Inputs are not latched. Note: 16 different Input/Output configurations are possible in this Mode.

5.2

Mode 1: Input or Output with Handshake

This mode provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “handshaking” signals. The features of this mode include the following: 1. Two ports (A and B) function as 8-bit I/O ports. They can be configured either as input or output ports. 2. Each port uses three lines from port C as handshake signals. The remaining two lines can be used for simple I/O functions. 6

5.2 Mode 1: Input or Output with Handshake 3. Input and output data are latched. 4. Interrupt logic is supported. Note: Mode 1 can be used either in Asynchronous mode (using handshaking signals) or in Interrupt-driven mode (using INTR signal). In 8255, the specific lines from Port C used for handshake signals vary according to the I/O function of a port. 5.2.1

Input

The associated control signals used for handshaking when ports A and B are configured as input ports are shown below.

PA7 – PA0

Connected to I/O device INTEA

STBA

PC4

IBFA

PC5

Connected to any one of the interrupt pins of µP (RST 7.5, RST 6.5, RST 5.5, INTR)

INTRA

PC3

PB7 – PB0

Connected to I/O device INTEB

STBB

PC2

IBFB

PC1

RD

Connected to any one of the interrupt pins of µP (RST 7.5, RST 6.5, RST 5.5, INTR)

INTRB

PC0

PC6,7

Simple I/O

Figure 5: 8255 Mode 1 Input Configuration

7

5.2 Mode 1: Input or Output with Handshake Let us first consider asynchronous data transfer and for the sake of brevity, we will explain using Port A. First STBA goes “low”, signifying that data has been transfered from the I/O device to 8255’s Port A. The 8255 in response to STBA will generate an IBFA “high” signal to indicate that it has received the data. After this, µP will generate RD signal to read the data from Port A. Once the read operation is completed, IBFA becomes inactive (goes “low”) and the I/O device can start sending the next data by making STBA “low”. In Interrupt-driven data transfer, first STBA goes “low”, signifying that data has been transfered from the I/O device to 8255’s Port A. The 8255 in response to STBA will generate an IBFA “high” signal to indicate that it has received the data. It will also generate an INTRA “high” signal (assuming INTEA flip-flop is set). This INTRA signal will interrupt the µP and as a consequence of this, the µP will jump to the corresponding Interrupt Service Sub-routine (ISS) address. The INTRA signal becomes inactive (goes “low”) and the µP performs a read operation to transfer the data from Port A to µP.

Timing Diagram STB

IBF INTR RD

Input from I/O Device

Figure 6: Input Timing Diagram for both Asynchronous and Interrupt-driven Data Transfer

8

5.2 Mode 1: Input or Output with Handshake Input Control Signals The functions of the control signals can be summarized as follows: • STB (Strobe Input): This signal (active low) is generated by an I/O device to indicate that it has transmitted a byte of data. • IBF (Input Buffer Full): This output signal is an acknowledgment by the 8255 to indicate that the input latch has received the data byte. This is reset when the µP reads the data. • INTR (Interrupt Request): This is an output signal which is used to interrupt the µP. This signal is generated if STB, IBF and INTE are all at logic 1. This is reset by the falling edge of the RD signal. • INTE (Interrupt Enable): This is an internal flip-flop used to enable or disable the generation of INTR signal. This is set or reset using PC4 (for INTEA ) or PC2 (for INTEB) in BSR mode.

Control Word D7

D6

D5

D4

D3

D2

D1

D0

1

0

1

1

1/0

1

1

X

I/O Mode

Port B Input

Port A Mode 1

Port B Mode 1

Port A Input

PC6 ,7 1 = Input 0 = Output

Figure 7: Mode 1 Input Control Word Format

9

5.2 Mode 1: Input or Output with Handshake 5.2.2

Output

The associated control signals used for handshaking when ports A and B are configured as output ports are shown below.

PA7 – PA0 Connected to I/O device OBFA

PC7 INTEA

ACKA

PC6

Connected to any one of the INTRA

PC3

interrupt pins of µP

(RST 7.5, RST 6.5, RST 5.5, INTR)

PB7 – PB0 WR Connected to I/O device OBFB

PC1

INTEB

ACKB

PC2

INTRB

PC0

Connected to any one of the interrupt pins of µP

(RST 7.5, RST 6.5, RST 5.5, INTR) PC4,5

Simple I/O

Figure 8: 8255 Mode 1 Output Configuration

10

5.2 Mode 1: Input or Output with Handshake Let us first consider asynchronous data transfer and for the sake of brevity, we will explain using Port B. First WR goes “low”, indicating that the µP has written some data onto 8255’s Port B. In response to this, 8255 will make OBFB “low”, which will tell the I/O device that new data is available. Once the I/O device has received the new data, it will generate an ACKB “low” signal and make OBFB signal inactive (“high”) to indicate that the output buffer is empty and that new data can be written by the µP. In Interrupt-driven data transfer, an interrupt causes the µP to write data. Once data has been written, the INTRB signal goes “low”. 8255 also makes OBFB signal “low”, which will tell the I/O device that new data is available. Once the I/O device has received the new data, it will generate an ACKB “low” signal and make OBFB signal inactive (“high”) to indicate that the output buffer is empty. 8255 will now generate an INTRB “high” signal (assuming INTEB flip-flop is set). This will interrupt the µP and as a consequence, the µP will jump to the corresponding ISS address and perform the next write instruction.

Timing Diagram WR

OBF INTR

ACK

Output

Figure 9: Output Timing Diagram for both Asynchronous and Interrupt-driven Data Transfer

11

5.2 Mode 1: Input or Output with Handshake Output Control Signals The functions of the control signals can be summarized as follows: • OBF (Output Buffer Full): This is an output signal that goes low when the µP writes data into the output latch of 8255. This signal indicates to an output peripheral that new data is ready to be read. • ACK (Acknowledge): This is an input signal from an I/O device that goes low to inform the 8255 that data from the port has been accepted. • INTR (Interrupt Request): This is an output signal which is used to interrupt the µP to request the next data. This signal is generated if OBF, ACK and INTE are all at logic 1. This is reset by the falling edge of the WR signal. • INTE (Interrupt Enable): This is an internal flip-flop used to enable or disable the generation of INTR signal. This is set or reset using PC6 (for INTEA ) or PC2 (for INTEB) in BSR mode.

Control Word

D7

D6

D5

D4

D3

D2

D1

D0

1

0

1

0

1/0

1

0

X

I/O Mode

Port B Output

Port A Mode 1

Port B Mode 1

Port A Output

PC4 ,5 1 = Input 0 = Output Figure 10: Mode 1 Output Control Word Format

12

5.3 Mode 2: Bidirectional Data Transfer

5.3

Mode 2: Bidirectional Data Transfer

This mode provides a means for communicating with a peripheral device on a single 8-bit bus for both transmitting and receiving data. The features of this mode include: 1. Port A is used as the bidirectional port. 2. Port B can be configured either in Mode 0 or Mode 1. 3. Port A uses five lines from Port C (PC3 to PC7 ) as handshaking signals. These are provided to maintain proper bus flow discipline. The remaining three lines (PC0 to PC2 ) can be used for simple I/O functions or as handshake for Port B. 4. Both inputs and outputs are latched. 5. Interrupt logic is supported.

Control Word

D7

D6

D5

D4

D3

D2

D1

D0

1

1

X

X

X

1/0 1/0 1/0 PC0−2 1 = Input 0 = Output

I/O Mode

Port A Mode 2 Port B 1 = Input 0 = Output Group B Mode 1 = Mode 1 0 = Mode 0

13

Summary D7 0/1

I/O Mode

BSR Mode For Port C No effect on I/O Mode

Mode 0 Simple I/O for ports A, B, and C

Mode 2

Mode 1 Handshake I/O for ports A and/or B

Bidirectional data bus for port A Port B: either Mode 0 or 1

6 Port C bits are used for handshake

5 Port C bits are used for handshake for Port A

2 Port C bits are used as Simple I/O

3 Port C bits are used as Simple I/O or handshake for Port B

Input

Output

Port A PC3,4,5

PC3,6,7

Port B PC0,1,2

PC0,1,2

Simple I/O PC6,7

PC4,5

Port A

Port B Mode 0

Port B Mode 1

PC3,4,5,6,7

PC0,1,2

PC0,1,2

Handshake for port A

Simple I/O

Handshake for port B

6

Examples

6.1 Write the instructions to incorporate the following settings in 8255 PPI. • Port A as a bidirectional port. • Port B as output port in Mode 0 • Rest pins of Port C as input ports. Given that, address of the Control Register is D3H

Calculating the control word: D7

D6

D5

D4

D3

D2

D1

D0

1

1

X

X

X

0

0

1 PC0−2 Input

I/O Mode

Port B output Port A Mode 2 Group B Mode 0

MVI A, 0C1H ; Control Word, assume ‘0’ as don’t care OUT 0D3H

; Control Word written to Control Register ; 8255 is now configured accordingly

15

6.2 Write the instructions to incorporate the following settings in 8255 PPI. • Port A as a bidirectional port. • Port B as output port in Mode 1 Given that, address of the Control Register is F3H

Calculating the control word: D7

D6

D5

D4

D3

D2

D1

D0

1

1

X

X

X

1

0

X Port B output

I/O Mode

Port A Mode 2

Group B Mode 1

MVI A, 0C4H ; Control Word, assume ‘0’ as don’t care OUT 0F3H

; Control Word written to Control Register ; 8255 is now configured accordingly

16

6.3 Write the instructions to set bits PC7 and PC3 and reset them after 10 ms. Assume DELAY subroutine is available, Control Register address is 83H.

Calculating the control words to set and reset PC7 and PC3 respectively: D7

D6

D5

D4

D3

D2

D1

D0 Control Word

BSR Mode

Don’t Care

Bit Select

Set/Reset

Set bit PC7

0

X

X

X

1

1

1

1

0FH

Set bit PC3

0

X

X

X

0

1

1

1

07H

Reset bit PC7

0

X

X

X

1

1

1

0

0EH

Reset bit PC3

0

X

X

X

0

1

1

0

06H

MVI A, 0FH

; Load byte in accumulator to set PC7

OUT 83H

; Set PC7 = 1

MVI A, 0FH

; Load byte in accumulator to set PC3

OUT 83H

; Set PC3 = 1

CALL DELAY

; This is a 10-ms delay

MVI A, 06H

; Load byte in accumulator to reset PC3

OUT 83H

; Reset PC3

MVI A, 0EH

; Load byte in accumulator to reset PC7

OUT 83H

; Reset PC7

17

6.4 Write the instructions to incorporate the following settings in 8255 PPI. • Port A as Input in Mode 1, interrupt-driven data transfer. • Port B as Output in Mode 1, asynchronous data transfer. Given that the address of the control register is FFH

For interrupt driven data transfer in Port A, INTEA has to be set. The corresponding bit is PC4 . Calculating the control word to initialize 8255: D7

D6

D5

D4

D3

D2

D1

D0

1

0

1

1

X
...