Xilinx 14.1 Guidelines PDF

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Guidelines for FPGA...

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Xilinx 14.1 Guidelines 1. Double click on the following icon of Xilinx 14.1

2. The following window will appear. Close the Tip of the Day

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3. Start the new project as follows:

File >> New Project

4. Give your project name such as:

First_Project

Change the default Location to some other location such as: D:\Xilinx Projects\First_Project Your top level source type must be:

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HDL

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5. Click Next 6. The following window will appear. Make sure your Simulator must be ISim. Forget about remaining options.

7. Click Next 8. The following window will appear, Click Finish.

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9. You can see your project name in Design Window as show below.

10. To add source file to your project, go to:

Xilinx 14.1 Manual

Project >> New Source

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11. In the New Source window select Verilog Module Give some file name to your source file: First_Project (Usually file name is same as that of your project name, but it can be different also.)

12. Click Next 13. The following window will appear, again Click Next. (You can also specify input and output of your module here.)

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14. Click Finish

15.You will see the following windows.

In Editing Window from Line # 2 to Line # 20 (comments lines), some information regarding project is given, just delete this. Xilinx 14.1 Manual

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16. Write some Verilog Code for your project in your module and Double Click on Synthesize-XST in Processing Window.

17. Again in Processing Window Double Click on Check Syntax to check syntax

error in code. Make sure that your Verilog Code is free of any Syntax errors.

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18. If you want to view the Block Diagram and Logical Diagram of your project double click on View RTL Schematic in processing Window.

19. Click on top-level block option and then click O.K.

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20. This is the Block Diagram of your project.

21. To view Logical Diagram of your project, double click on Block Diagram.

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22. Moving to simulate the Verilog module for First_Project. Go to: Project >> New Source

23. In New Source Window, select Verilog Test Fixture and give some file name and then Click Next.

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24. Again Click Next

25. Click Finish

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26. The following window will appear. Click on Simulation in Design Window.

27. Select your file in Design Window and then double click on Simulate Behavioral Model

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28. This is your timing diagram.

29. You can apply different input combinations by using Force Constant and Force Clock options. But How?........ Explore it yourself.

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30. Here is the final timing diagram by using different input combinations.

That’s it !

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