10. Verification of Full Adder PDF

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LAB MANUAL

Digital Logic Design

Name: Sameer Ahmed CMS ID: 50246

Lab No. 10 VERIFICATION OF FULL ADDER CIRCUIT 

Objective: To analyze the operation of Full Adder Circuit using IC 74HCT86 (X-OR), 7432 (OR) and 7408 (AND).



Components: -

IC 74HCT86 (The device containing four independent XOR gates). IC 7408 (The device containing four independent AND gates). IC 7432 (The device containing four independent OR gates).

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Tools: - ETS-7000 Trainer - Breadboard - Jumpers - Proteus Software

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Theory: Full adder is a combinational arithmetic circuit of X-OR gates, OR gate and AND gates, that adds three inputs and produces two outputs. The first two inputs are A and B and the third input is known as Carry (C-IN). The output carry is designated as C-OUT and the normal output is designated as S which is SUM. A Full adder circuit can be constructed by using two half adder circuits added together with an OR gate. The first half adder circuit is provided with two single bit binary inputs A and B. As we have proved before, it will produce two outputs, SUM and Carry out. First half adder circuit’s SUM output is further provided to the second half adder circuit’s input. We provided the carry in bit across the other input of second half order circuit. Again it will provide SUM out and Carry out bit. This SUM output is the final output of the Full adder circuit. On the other hand the Carry out of First half adder circuit and the Carry out of second adder circuit is further provided into OR logic gate. After logic OR of two Carry output, we get the final carry out of full adder circuit.

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Procedure: The Trainer Board uses LEDs as an indicator for the logical behavior of the Circuit. One LED for Sum and the other LED for Carry output Thus, by connecting any of the input of these legs to the input switch on the trainer, making the connection between these gates as shown in the circuit diagram, connecting the output leg of these gates with the LEDs on the trainer, the 7th leg with the ground and the 14th leg with the supply of all gates, we can check the behavior of a Full Adder Circuit. The ON condition (1) of Carry OUT LED will be indicated in the form of radiation of light only when two of the three or all of the inputs are ON (1), similarly The ON condition (1) of Sum LED will be indicated in the form of radiation of light only if all of the inputs are HIGH (1) or any one of the three input is HIGH (1).

36

LAB MANUAL



Digital Logic Design

Name: Sameer Ahmed CMS ID: 50246

Truth Table:

INPUTS



OUTPUTS

A

B

CARRY IN

SUM “S”

CARRY OUT

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

Block Diagram of FULL ADDER Circuit:

Figure 1: Block Diagram of the Full Adder Circuit



Logic Diagram of FULL ADDER Circuit:

Figure 2: Circuit of Full Adder Circuit.

37

LAB MANUAL

Digital Logic Design

Name: Sameer Ahmed CMS ID: 50246

 Circuit Simulation Using Proteus Software: 

Case 1: o A=0, B=0, C=0

Figure 3: Case 1 of the Full Adder Circuit.



Case 2: o A=0, B=0, C=1

Figure 4: Case 2 of the Full Adder Circuit.

38

LAB MANUAL



Digital Logic Design

Name: Sameer Ahmed CMS ID: 50246

Case 3: o A=0, B=1, C=0

Figure 5: Case 3 of the Full Adder Circuit.



Case 4: o A=0, B=1, C=1

Figure 6: Case 4 of the Full Adder Circuit.

39

LAB MANUAL



Digital Logic Design

Name: Sameer Ahmed CMS ID: 50246

Case 5: o A=1, B=0, C=0

Figure 7: Case 5 of the Full Adder Circuit.



Case 6: o A=1, B=0, C=1

Figure 8: Case 6 of the Full Adder Circuit.

40

LAB MANUAL



Digital Logic Design

Name: Sameer Ahmed CMS ID: 50246

Case 7: o A=1, B=1, C=0

Figure 9: Case 7 of the Full Adder Circuit.



Case 8: o A=1, B=1, C=1

Figure 10: Case 8 of the Full Adder Circuit.

41

LAB MANUAL

Digital Logic Design

Name: Sameer Ahmed CMS ID: 50246

 Working on IDL-400 Trainer:

Figure 11: Practical work observations.

 123-

Precautions: Check all the VCC and GND at the pins 14 and 7 of the IC. Check all the wires and connections. Properly check all the gates if one gate is not working.

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