7 segment display Lab 4 - nill PDF

Title 7 segment display Lab 4 - nill
Author FAseeh Malik
Course Electronics II
Institution COMSATS University Islamabad
Pages 9
File Size 666.9 KB
File Type PDF
Total Downloads 85
Total Views 136

Summary

nill...


Description

Name: Fatma Alshammari Course Name: EE/CS 327 Laboratory Assignment 4 Objective: In this lab, we design and implement BCD to 7-Segment decoder. The Seven segment display is most frequently used the digital display in calculators, digital counters, digital clocks, measuring instruments, etc. Usually, the displays like LED’s as well as LCD’s are used to display the characters as well as numerical numbers. But, a seven segment display is used to display both the numbers and characters. These displays are frequently driven by the output phases of digital integrated circuits like decade counters as well as latches. However the outputs of these are in the type of 4-bit BCD (Binary Coded Decimal), so not appropriate for directly operating the seven segment display. For that, a display decoder can be employed for converting BCD code to seven segment code. Generally, it has four input lines as well as seven output lines. This article discusses how to design a BCD to seven segment display decoder circuit using logic gates. BCD to 7-Segment Decode 7-Segment Display: A seven-segment display (SSD) is a form of the electronic display device for displaying decimal numerals. The seven elements of the display can be selected in different combinations to represent the decimal numerals. Often the seven segments are arranged in an oblique (slanted) arrangement, which aids readability. Seven-segment displays may use a light-emitting diode (LED) or a liquid crystal display (LCD), for each segment, or other light- generating or controlling techniques. There are two types of simple LED package 7Segment display:  

Common Anode Common Cathode

The Common Cathode Display (CCD): In the common cathode display, all the cathode connections of the LED’s are joined together to logic “0” or ground. The individual segments are illuminated by application of a “HIGH”, logic “1” signal to the individual Anode terminals.

The Common Anode Display (CAD): In the common anode display, all the anode connections of the LED’s are joined together to logic “1” and the individual segments are illuminated by connecting the individual Cathode terminals to a “LOW”, logic “0” signal. Common Cathode and Common Anode Format:

Electrical connection of the individual diodes for a common cathode display and a common anode display and by illuminating each light emitting diode individually, they can be made to display a variety of numbers or characters. Segment Display Format:

So in order to display the number “3” for example, segments a, b, c, d and g would need to be illuminated. If we wanted to display a different number or letter then a different set of segments would need to be illuminated. Then for a 7-segment display, we can produce a truth table giving the segments that need to be illuminated in order to produce the required character.

BCD to 7-Segment Display Decoders: A binary coded decimal (BCD) to 7-segment display decoder such as the TTL 74LS47 or 74LS48, have 4 BCD inputs and 7 output lines, one for each LED segment. This allows a

smaller 4-bit binary number (half a byte) to be used to display all the denary numbers from 0 to 9 and by adding two displays together, a full range of numbers from 00 to 99 can be displayed with just a single byte of eight data bits. BCD to 7-Segment Decoder:

Truth Table for a 7-segment display

7-Segment Display Elements for all Numbers. A 7 Segmen t 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 1 9 1 U 1 U 1 U 1 U 1 U 1 U 1 K-Map for a:

B

C

D

a

b

c

d

e

f

g

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 1 0 0 1 0 0 0 0 0 1 1 1 1 1 1

0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0

0 1 0 1 1 1 0 1 0 1 0 0 0 0 0 0

0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0

1

AB/CD

00

01

11

10

00

0

1

0

0

1 0 0 0 0 0 1 0 0 1 1 1 1 1 1

01

1

0

0

0

11

1

1

1

1

10

0

0

1

1 K-Map for b: AB/CD 00

01

11

10

00

0

0

0

0

01

0

1

1

0

11

0

0

0

0

10

0

0

0

0

K-Map for c: AB/CD

00

01

11

10

00

0

0

1

0

01

0

0

0

0

11

0

0

0

0

10

0

0

0

0 K-Map for d:

K-Map for e: AB/CD

00

01

11

10

00

0

1

0

1

AB/CD

00

01

11

10

00

0

1

0

0

01

1

0

0

1

11

0

0

0

0

10

0

0

0

0

01

1

1

0

1

11

0

0

0

0

10

0

1

0

0 K-Map for f: AB/CD

00

01

11

10

00

0

1

1

1

01

0

0

0

1

11

0

0

0

0

10

0

0

0

0

K-Map for g: AB/CD

00

01

11

10

00

1

1

0

0

01

0

0

0

1

11

1

1

1

1

10

0

0

1

1

By using K-Map the expression for a, b, c, d, e, f, and g are given below a = A` B` C` D + B C` D` + A B + A C b= A` B D c=A` B` C D

d=A` B` C` D + A` B D` e=B` C` D + A` C D` + A` B C` f= A` B` D + A` C D` g= A` B` C` + B C D` + A B + A C

Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; -------------------------------------------------------------entity bcd_to_7seg is -------------------------------------------------------------Port ( A1,B1,C1,D1 : in STD_LOGIC; a,b,c,d,e,f,g : out STD_LOGIC); end bcd_to_7seg; ------------------------------------------------------------architecture Behavioral of bcd_to_7seg is -------------------------------------------------------------begin a...


Similar Free PDFs