74HC08 - Datasheet para circuito integrado PDF

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INTEGRATED CIRCUITS

DATA SH EET

74HC08; 74HCT08 Quad 2-input AND gate Product specification Supersedes data of 1990 Dec 01

2003 Jul 25

Philips Semiconductors

Product specification

Quad 2-input AND gate

74HC08; 74HCT08

DESCRIPTION

FEATURES

The 74HC/HCT08 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT08 provide the 2-input AND function.

Complies with JEDEC standard no. 8-1A ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. Specified from 40 to +85 C and 40 to +125 C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns. SYMBOL

PARAMETER

CONDITIONS

tPHL/tPLH CI

propagation delay nA, nB to nY input capacitance

CL = 15 pF; VCC = 5 V

CPD

power dissipation capacitance per gate

notes 1 and 2

TYPICAL 74HC08

74HCT08

7 3.5

11 3.5

ns pF

10

20

pF

Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD

VCC2

fi

VCC2

N + (CL

fo) where:

fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL

VCC2

fo) = sum of the outputs.

2. For 74HC08: the condition is VI = GND to VCC. For 74HCT08: the condition is VI = GND to VCC

1.5 V.

FUNCTION TABLE INPUT

OUTPUT

nA

nB

nY

L

L

L

L

H

L

H H

L H

L H

Note 1. H = HIGH voltage level; L = LOW voltage level.

2003 Jul 25

2

UNIT

Philips Semiconductors

Product specification

Quad 2-input AND gate

74HC08; 74HCT08

ORDERING INFORMATION TYPE NUMBER

PACKAGE TEMPERATURE RANGE

PINS

PACKAGE

MATERIAL

CODE

74HC08N

40 to +125 C

14

DIP14

plastic

SOT27-1

74HCT08N

40 to +125 C

14

DIP14

plastic

SOT27-1

74HC08D 74HCT08D

40 to +125 C 40 to +125 C

14 14

SO14 SO14

plastic plastic

SOT108-1 SOT108-1

74HC08DB

40 to +125 C

14

SSOP14

plastic

SOT337-1

74HCT08DB

40 to +125 C

14

SSOP14

plastic

SOT337-1

74HC08PW 74HCT08PW

40 to +125 C 40 to +125 C

14 14

TSSOP14 TSSOP14

plastic plastic

SOT402-1 SOT402-1

74HC08BQ

40 to +125 C

14

DHVQFN14

plastic

SOT762-1

74HCT08BQ

40 to +125 C

14

DHVQFN14

plastic

SOT762-1

PINNING PIN

SYMBOL

DESCRIPTION

1

1A

data input

2 3

1B 1Y

data input data output

4

2A

data input

5 6

2B 2Y

data input data output

7

GND

ground (0 V)

8

3Y

data output

9 10

3A 3B

data input data input

11

4Y

data output

12

4A

data input

13 14

4B VCC

data input supply voltage

2003 Jul 25

3

Philips Semiconductors

Product specification

Quad 2-input AND gate

74HC08; 74HCT08

handbook, halfpage handbook, halfpage

1A

1

14 VCC

1B

2

13 4B

1Y

3

12 4A

2A

4

2B

5

10 3B

2Y

6

9 3A

GND

7

8 3Y

11 4Y

08

1A

VCC

1

14

1B

2

13

4B

1Y

3

12

4A

2A

4

11

4Y

2B

5

10

3B

2Y

6

9

3A

MNA220

GND(1)

Top view

7

8

GND

3Y

MCE183

(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.

Fig.1

Pin configuration DIP14, SO14 and (T)SSOP14.

Fig.2 Pin configuration DHVQFN14.

handbook, halfpage

1

&

3

&

6

&

8

&

11

2 handbook, halfpage

1

1A

2

1B

4

2A

5

2B

9

3A 3B

10 12

4A

13

4B

1Y

3

2Y

6

3Y

8

4

4Y

5

9 10

11

12

MNA222

13 MNA223

Fig.4 IEC logic symbol.

Fig.3 Logic symbol.

2003 Jul 25

4

Philips Semiconductors

Product specification

Quad 2-input AND gate

74HC08; 74HCT08

handbook, halfpage

A handbook, halfpage

A

Y B

Y B

MNB037

Fig.5 HC logic diagram (one gate).

MNA221

Fig.6 HCT logic diagram (one gate).

RECOMMENDED OPERATING CONDITIONS SYMBOL

PARAMETER

74HC08

CONDITIONS

UNIT

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

5.0

6.0 VCC

4.5 0

5.0

5.5 VCC

V V

VCC

0

VCC

V

VCC VI

supply voltage input voltage

2.0 0

VO

output voltage

0

Tamb

ambient temperature

tr, tf

input rise and fall times

see DC and AC characteristics per device VCC = 2.0 V

74HCT08

40

VCC = 4.5 V

+25

+125

6.0

500

40

+25

+125

6.0

500

C

1000

VCC = 6.0 V

ns ns

400

ns

LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL

PARAMETER

CONDITIONS

MIN. 0.5

MAX.

VCC

supply voltage

IIK

input diode current

VI < 0.5 V or VI > VCC + 0.5 V

20

mA

IOK

output diode current

VO < 0.5 V or VO > VCC + 0.5 V

20

mA

IO ICC, IGND

output source or sink current VCC or GND current

25 50

mA mA

Tstg

storage temperature

+150

C

Ptot

power dissipation DIP14 package other packages

0.5 V < VO < V CC + 0.5 V 65 Tamb = 40 to +125 C; note 1 Tamb = 40 to +125 C; note 2

Notes 1. For DIP14 packages: above 70 C derate linearly with 12 mW/K. 2. For SO14 packages: above 70 C derate linearly with 8 mW/K. For SSOP14 and TSSOP14 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 C derate linearly with 4.5 mW/K. 2003 Jul 25

5

+7.0

UNIT

750 500

V

mW mW

Philips Semiconductors

Product specification

Quad 2-input AND gate

74HC08; 74HCT08

DC CHARACTERISTICS Family 74HC08 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL

PARAMETER

TEST CONDITIONS OTHER

MIN.

TYP.

MAX.

UNIT

VCC (V)

Tamb = 25 C VIH

VIL

VOH

VOL

ILI IOZ ICC

2003 Jul 25

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

2.0

1.5

1.2

V

4.5 6.0

3.15 4.2

2.4 3.2

V V

2.0

0.8

0.5

V

4.5

2.1

1.35

V

6.0

2.8

1.8

V

VI = VIH or VIL IO = 20 A

2.0

1.9

IO = 20 A

4.5

4.4

4.5

V

IO = 4.0 mA IO = 20 A

4.5 6.0

3.98 5.9

4.32 6.0

V V

IO = 5.2 mA

6.0

5.48

5.81

V

VI = VIH or VIL IO = 20 A IO = 20 A

2.0 4.5

2.0

0 0

V

0.1 0.1

V V

IO = 4.0 mA

4.5

0.15

0.26

V

IO = 20 A

6.0

0

0.1

V

6.0 6.0

0.16 0.1

0.26 .0.1

V A

.0.5

A

IO = 5.2 mA VI = VCC or GND

input leakage current 6.0 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current VI = VCC or GND; IO = 0 6.0

6

2

A

Philips Semiconductors

Product specification

Quad 2-input AND gate

SYMBOL

PARAMETER

74HC08; 74HCT08

TEST CONDITIONS OTHER

VCC (V)

MIN.

TYP.

MAX.

UNIT

Tamb = 40 to +85 C VIH

VIL

VOH

VOL

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

2.0

1.5

V

4.5 6.0

3.15 4.2

V V

2.0

0.5

V

4.5

1.35

V

6.0

1.8

V

VI = VIH or VIL IO = 20 A

2.0

1.9

V

I O = 20 A

4.5

4.4

V

I O = 4.0 mA I O = 20 A I O = 5.2 mA

4.5 6.0

3.84 5.9

V V

6.0

5.34

V

VI = VIH or VIL IO = 20 A IO = 20 A

2.0 4.5

0.1 0.1

V V

IO = 4.0 mA

4.5

0.33

V

IO = 20 A

6.0

0.1

V

ILI

input leakage current

6.0 6.0

0.33 1.0

V A

IOZ

6.0 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current VI = VCC or GND; IO = 0 6.0

.5.0

A

ICC

2003 Jul 25

IO = 5.2 mA VI = VCC or GND

7

20

A

Philips Semiconductors

Product specification

Quad 2-input AND gate

SYMBOL

PARAMETER

74HC08; 74HCT08

TEST CONDITIONS OTHER

VCC (V)

MIN.

TYP.

MAX.

UNIT

Tamb = 40 to +125 C VIH

VIL

VOH

VOL

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

2.0

1.5

V

4.5 6.0

3.15 4.2

V V

2.0

0.5

V

4.5

1.35

V

6.0

1.8

V

VI = VIH or VIL IO = 20 A

2.0

1.9

V

I O = 20 A

4.5

4.4

V

I O = 4.0 mA I O = 20 A I O = 5.2 mA

4.5 6.0

3.7 5.9

V V

6.0

5.2

V

VI = VIH or VIL IO = 20 A IO = 20 A

2.0 4.5

IO = 4.0 mA

4.5

0.4

V

6.0

0.1

V

6.0 6.0

0.4 1.0

V A

IO = 5.2 mA VI = VCC or GND

input leakage current

IOZ

6.0 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current VI = VCC or GND; IO = 0 6.0

2003 Jul 25

V V

IO = 20 A ILI

ICC

0.1 0.1

8

10.0 40

A A

Philips Semiconductors

Product specification

Quad 2-input AND gate

74HC08; 74HCT08

Family 74HCT08 At recommended operating conditions; voltages are referenced to GND (ground = 0). SYMBOL

PARAMETER

TEST CONDITIONS OTHER

MIN.

TYP.

MAX.

UNIT

VCC (V)

Tamb = 25 C VIH VIL

HIGH-level input voltage

4.5 to 5.5

LOW-level input voltage

4.5 to 5.5

VOH

HIGH-level output voltage

VOL

LOW-level output voltage

VI = VIH or VIL IO = 20 A IO = 4.0 mA

4.5 4.5

VI = VIH or VIL IO = 20 A IO = 4.0 mA

4.5 4.5 5.5

ILI

input leakage current

VI = VCC or GND

IOZ

3-state output OFF current

ICC

quiescent supply current

5.5 VI = VIH or VIL; VO = VCC or GND; IO = 0 VI = VCC or GND; 5.5 IO = 0 VI = VCC 2.1 V; 4.5 to 5.5 IO = 0

ICC

additional supply current per input

2.0

1.6 1.2

4.4 3.84

V 0.8

4.5 4.32 0 0.15

60

V V V

0.1 0.26

V V

0.1

A

0.5

A

2

A

216

A

Tamb = 40 to +85 C VIH

HIGH-level input voltage

4.5 to 5.5

VIL

LOW-level input voltage

4.5 to 5.5

VOH

HIGH-level output voltage

VOL

LOW-level output voltage

ILI

input leakage current

IOZ

3-state output OFF current

ICC

quiescent supply current

ICC

2003 Jul 25

additional supply current per input

2.0

V 0.8

V

VI = VIH or VIL IO = 20 A IO = 4.0 mA

4.5 4.5

VI = VIH or VIL IO = 20 A

4.5

0.1

V

IO = 4.0 mA VI = VCC or GND

4.5 5.5

0.33 1.0

V A

5.0

A

5.5 VI = VIH or VIL; VO = VCC or GND; IO = 0 VI = VCC or GND; 5.5 IO = 0 VI = VCC 2.1 V; 4.5 to 5.5 IO = 0

9

4.4 3.84

V V

20

A

270

A

Philips Semiconductors

Product specification

Quad 2-input AND gate

SYMBOL

PARAMETER

74HC08; 74HCT08

TEST CONDITIONS OTHER

MIN.

TYP.

MAX.

UNIT

VCC (V)

Tamb = 40 to +125 C VIH

HIGH-level input voltage

4.5 to 5.5

VIL

LOW-level input voltage

4.5 to 5.5

VOH

HIGH-level output voltage

VI = VIH or VIL IO = 20 A IO = 4.0 mA

VOL

LOW-level output voltage

V

4.5

3.7

V

VI = VIH or VIL IO = 20 A

4.5

0.1

V

IO = 4.0 mA

4.5

0.4

V

5.5

input leakage current

IOZ

3-state output OFF current

ICC

quiescent supply current

5.5 VI = VIH or VIL; VO = VCC or GND; IO = 0 VI = VCC or GND; 5.5 IO = 0 VI = VCC 2.1 V; 4.5 to 5.5 IO = 0

2003 Jul 25

V

4.4

ILI

additional supply current per input

V 0.8

4.5

VI = VCC or GND

ICC

2.0

10

1.0

A

10

A

40

A

294

A

Philips Semiconductors

Product specification

Quad 2-input AND gate

74HC08; 74HCT08

AC CHARACTERISTICS Family 74HC08 GND = 0 V; tf = tf = 6 ns; CL = 50 pF. SYMBOL

PARAMETER

TEST CONDITIONS WAVEFORMS

VCC (V)

MIN.

TYP.

MAX.

UNIT

Tamb = 25 C t PHL/tPLH

t THL/tTLH

propagation delay nA, nB to nY

see Figs 7 and 8 2.0

output transition time

see Figs 7 and 8 2.0

4.5 6.0

25

90

ns

9 7

18 15

ns ns

19

75

ns

4.5

7

15

ns

6.0

6

13

ns

115

ns

23

ns

20 95

ns ns

4.5

19

ns

6.0

16

ns

135 27

ns ns

23

ns

Tamb = 40 to +85 C tPHL/tPLH

tTHL/tTLH

propagation delay nA, nB to nY output transition time

see Figs 7 and 8 2.0 4.5 6.0 see Figs 7 and 8 2.0

Tamb = 40 to +125 C tPHL/tPLH

propagation d...