AHB SRAM Interface Design spec rev PDF

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Summary

this is the project description of interfacing of ahb protocol with the external sram...

Description

AHB to External SRAM Interface Revision - 1

Table of Content Sr. No

Content

Page No.

1.

Introduction

2

2.

AHB Master and Slave section

3

Operation

3

Signal Description

4

Register Configuration

6

Memory Configuration Register

6

Memory Transfer Configuration Register

7

Memory Timing Configuration Register

8

Timing Diagram (1-Turnaround cycle)

9

Timing Diagram (2-Turnaround cycle)

10

3.

4.

1

1. Introduction The AHB SRAM Interface provides a standard AHB interface to translate AHB bus reads and writes operation into reads and writes with the signaling and timing of a standard 32-bit SRAM. This interface module enables external SRAM, static memory device or external peripherals to connect to the cortex-M processor design. Features 1.

AMBA - AHB Compatible

2.

Handles byte, half, and word (8,16,32bit) accesses

3.

Can be used with external Memory

4.

Read write operation with wait state

Architecture The figure below shows the overall structure of the core.

Fig.1 Architecture of ARM processor

2. AHB Master with Slave The AHB SRAM Controller contains two interfaces: an AHB Slave interface (for connecting to a Interconnect - Slave interface of an AHB Channel module), and a Memory interface (for connecting to a standard synchronous SRAM).

2

AHB MASTER

MEMORY CONTROLLER

Master section |

Slave section

SRAM

Fig.2 Master and Slave inter-connection diagram

HCLK

ADDR [AW-1:0]

HRESETn

DATAOUT [15:0]

HSEL HADDR [AW-1:0] HTRANS [1:0] HSIZE [2:0]

AHB

DATAOEn DATAIN [15:0]

to

HWRITE HREADY

SRAM

HWDATA [31:0] HREADYOUT

WEn

HRESP HRDATA [31:0]

OEn CEn

CFGREADYCLE [2:0] LBn CFGWRITECYCLE [2:0] CFGTURNAROUNDCYCLE [2:0]

UBn

CFGSIZE

Fig.3 AHB with external SRAM Interface 2.1 Operation The interface module is designed to support an external bidirectional data bus. Tri-state buffer is used to control the bidirectional operation with data output enable signal. They also contain chip enable, 3

output enable and external write enable signal to control the rea d and write operation with the slave device. The design enables turnaround cycles to be inserted between reads and write to prevent current spike that could occur for a very short time when the processor system and the external device both drive the data bus. They contain configuration signals control wait state for read, wait state for write and the number of turnaround cycles respectively. 2.2 Signal Description - AHB Signals Signal HCLK

Direction

Width

Input

1

Description AHB source Clock. The bus clock times all bus transfers. All signal timings are related to the rising edge of HCLK.

HRESETn

Input

1

The bus reset signal is active LOW and resets the system and the bus. This is the only active LOW signal. Each slave has its own slave select signal HSELx and this signal indicates that the current transfer is intended for the selected slave.

HSELx

Input

1

When the slave is initially selected, it must also monitor the status of HREADY to ensure that the previous bus transfer has completed, before it responds to the current transfer.

HADDR [AW-1:0]

Input

16 / 32

The 32-bit system addresses bus. Default is 16 Indicates the transfer type of the current transfer. This can be: • IDLE

HTRANS [1:0]

Input

2

• BUSY • NONSEQUENTIAL • SEQUENTIAL. Indicates the size of the transfer, that is typically byte, halfword,

HSIZE [2:0]

Input

3

or word. The protocol allows for larger transfer sizes up to a maximum of 1024 bits. Indicates the transfer direction. When HIGH this signal indicates a write transfer and when LOW a read transfer.

HWRITE

Input

1

It has the same timing as the address signals, however, it must remain constant throughout a burst transfer.

HREADY

Input

1

HWDATA [31:0]

Input

32

When HIGH, the HREADY signal indicates to the master and all slaves, that the previous transfer is complete. The write data bus transfers data from the master to the slaves during write operations.

4

Signal

Direction

Width

Description A minimum data bus width of 32 bits is recommended. However, this can be extended to enable higher bandwidth operation. When HIGH, the HREADYOUT signal indicates that a transfer

HREADYOUT

Output

has finished on the bus.

1

This signal can be driven LOW to extend a transfer. Transfer response, selected by the decoder. The transfer response, after passing through the multiplexor, provides the master with additional information on the status of a transfer. HRESP

Output

When LOW, the HRESP signal indicates that the transfer status

1

is OKAY. When HIGH, the HRESP signal indicates that the transfer status is ERROR. HRDATA [31:0]

Output

Read data from the selected slave.

32

Memory interface signals Signal

Direction

Width

CFGREADYCYCLE

Input

3

CFGWRITECYCLE

Input

3

Description No. of clock cycles after read operation. The signal value “0” indicates one read cycle. No. of clock cycles for a write operation. The signal value “0” indicates one write cycle. No. of clock cycles required to switch between a

CFGTURNAROUNDCYCLE

Input

3

read and write operation on the tri-state data bus. The signal value “0” indicates one turnaround cycle.

CFGSIZE

Input

1

If value set to ‘0’ indicates 8-bit memory. If value set to ‘1’ indicates 16-bit memory.

Output from Interface The 16-bit address bus to address the memory

ADDR [AW-1:0]

Output

16

DATAOUT [15:0]

Output

16

16-bit data read from the memory.

DATAIN [15:0]

Input **

16

16-bit data written to the memory.

DATAOEn

Output

WEn

Output

1

Write strobe signal.

OEn

Output

1

Read access output enable signal.

location.

Tristate buffer output enable for DATAOUT.

5

CEn

Output

1

Chip enable.

LBn

Output

1

Lower byte enable.

UBn

Output

1

Upper byte enable.

** Output of SRAM (slave output) 3. Register Configuration All the registers inside the memory interface are described below. Name MC – Memory Config. MTC – Memory transfer Config. MTR – Memory Timing Register Config.

Addr. 0x00

Width 32

Access RW

Description Main memory configuration register

0x04

32

RW

Memory transfer control register

0x08

32

RW

Memory Cycle Config. Register

The interface includes configuration register and memory address spaces. The address range for each of them can be individual selected by defining them separately. The define statement below, specifies the address decoding for registers. `define

MC_REG_SEL

(addr_sel_i [31:29] == 3’h7)

In this case address line 31:29 must be all one to access the configuration registers. The next defines the statement specifies the address decoding for all chip selects and the attached devices. `define

MC_MEM_SEL

(addr_sel_i[31:29] == 3’h0)

In this case address line 31:29 must be all zeros to access the configuration registers. 3.1 MC – Memory Configuration register. The MC register is used to configure the type of memory connected with the interface. Also it has chip select signal which selects the desired chip for read and write operation. The memory Width selects the width of the memory bus. 32

6 Reserved

Bits 32 : 6 5:4

Name Reserved Memory Width

5

4 3

Mem_width

2

Mem_type

1

0 CS

Function Reserved for future use. 00 – 8 bits 01 – 16 bits 10 – 32 bits 11 – reserved 6

3:2

Memory type

1:0

Chip select

00 – Reserved 01 – SRAM 10 – NAND 11 – Reserved 00 – chip 1 01 – chip 2 10 – chip 3 11 – chip 4

3.2 MTC - Memory transfer control register 32

10 Reserved

9

7 6 Burst align

4 No. of Bytes

3

1 Burst length

0 Read/write

This register control the burst transfer in both read and write operation. A WRAP burst is similar to INCR burst. In WRAP the address will be incremented based the SIZE, but on reaching the upper address limit address will wrap to lower address. There are restrictions on WRAP bursts, - The start address must be aligned to the size of each transfer - The length of the burst must be 2, 4, 8, or 16 transfers Below equations are used for WRAP address calculation: Lower address limit: Wrap_Boundary = (INT(Start_Address/(Number_Bytes×Burst_Length)))× (Number_Bytes×Burst_Length) Upper address limit: Address = Wrap_Boundary + (Number_Bytes × Burst_Length) Bits

Name

Function

32 : 10

Reserved

Reserved for future use.

9:7

Burst align

These bits determine whether memory bursts are split on memory burst boundaries: 000 = bursts can cross any address boundary 001 = burst split on memory burst boundary, that is, 32 beats for continuous 010 = burst split on 64 beat boundary 011 = burst split on 128 beat boundary 100 = burst split on 256 beat boundary Others = reserved. 7

6:4

Byte size

b00 – 8 bits b01 – 16 bits b10 – 32 bits b11 – reserved

3 :1

Burst length

b000 – 1 beat b001 – 4 beat b010 – 8 beat b011 – 16 beat b100 – 32 beat b101 – continuous b110 – b111 – reserved

0

Read / write

If value is ‘1’ performs Read operation and for ‘0’ performs Write operation.

3.3 MTR - Memory Timing Register configuration The timing configuration registers configures the number of clock cycles required for read and write operation. Interface adds one additional clock cycle for write operation, before as setup cycle and after as hold cycle. 32

10 Reserved Bits

9

8

CFS Name

32 : 10

Reserved

9

CFGSIZE

8:6 5:3 2:0

CFGTURNAROUNDCYCLE CFGWRITECYCLE CFGREADCYCLE

6 5 TR

3 WC

2

0 RC

Function Reserved Set ‘1’ for 8-bit memory and ‘0’ for 16-bit memory No. of clock cycle between read and write No. of clock cycle for write operation No. of clock cycle for read operation

8

Timing diagram

Fig.4 Read and write operation

9

Fig.5 Read and write operation with 2 turnaround state 1. The master drives the address and control signals onto the bus after the rising edge of HCLK. 2. The slave then samples the address and control information on the next rising edge of HCLK. 3. After the slave has sampled the address and control it can start to drive the appropriate HREADYOUT response. This response is sampled by the master on the third rising edge of HCLK.

10

Revision–1 1. Changed Interface and Timing diagram. 2. Added table of content. 3. Changed document alignment.

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