AICS - Analogue Integrated Circuits PDF

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TABLE OF CONTENTSLIST OF FIGURES LIST OF FIGURES 1 INTRODUCTION 2 OBJECTIVE 3 DESIGN OF MULTI-STAGE MOS OPERATIONAL AMPLIFIER 3 Calculation 4 SIMULATION RESULTS DC Analysis AC Analysis 5 DISCUSSION 6 CONCLUSION Figure 1: Multistage MOS Operational Amplifier..............................................

Description

TABLE OF CONTENTS

LIST OF FIGURES ........................................................................................................................ 2 1.0

INTRODUCTION ............................................................................................................... 3

2.0

OBJECTIVE ........................................................................................................................ 4

3.0

DESIGN OF MULTI-STAGE MOS OPERATIONAL AMPLIFIER ................................ 4

3.1 4.0

Calculation ....................................................................................................................... 5 SIMULATION RESULTS .................................................................................................. 9

DC Analysis ................................................................................................................................ 9 AC Analysis .............................................................................................................................. 10 5.0

DISCUSSION .................................................................................................................... 14

6.0

CONCLUSION .................................................................................................................. 15

LIST OF FIGURES Title

Page No.

Figure 1: Multistage MOS Operational Amplifier………………………………………………... 4 Figure 2: Differential Pair Stage…………………………………………………………..……… 5 Figure 3: Common Drain Stage……………………………………………………………...…… 7 Figure 4: Common Source Stage…………………………………………………………………. 8 Figure 5: DC Sweep of the Differential Amplifier……………………………………..………… 9 Figure 6: DC Sweep of the Common Source Stage…………………………………...………… 10 Figure 7: Gain for the differential pair stage……………………………………………………. 10 Figure 8: Gain for the common source stage……………………………………………………. 11 Figure 9: Overall gain…………………………………………………………………………… 11 Figure 10: Input transient response……………………………………………………………… 12 Figure 11: Output transient response……………………………………………………………. 12 Figure 12: DC operating point value…………………………………………………………….. 13

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1.0

INTRODUCTION The Metal Oxide Semiconductor Field Effect Transistor, MOSFET is the most commonly

used transistor in both digital and analog circuits. The MOSFET differential amplifier is used in integrated circuits such as operational amplifiers where they provide a high input impedance at the input terminals. A well designed differential amplifier differential amplifier with its current mirror biasing stages is made of corresponding pair devices to reduce the disproportions from one side of the differential amplifier to another. The source and drain of the MOSFET is where the charge enters and leaves respectively. The gate of the MOSFET located in between the source and drain controls the width of the channel where the charge is carried. A MOSFET can be used in fast switching applications. The depletion mode in the MOSFET produces maximum conductance but when the gate voltage decreases, the channel conductivity increases depending on the type of material used. On the other hand, the enhancement mode is where the gate voltage is not present which results to a not purposeful MOSFET.

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2.0

OBJECTIVE The objective of this lab is to design, simulate and analyze a multi-stage MOS operational

amplifier to drive a capacitive load and a resistive load. The amplitude has to be designed for maximum gain and bandwidth but at a limited power budget, power supplies and load capacitance. In order to complete the following simulation, a few conditions have to be considered such as using any SPICE simulator to produce the results, using the appropriate TSMC CMOS technology to acquire the preferred requirement and to perform the essential calculations. Finally, the Transient Response, DC & AC analysis results have to be identified in this simulation. The amplifier must achieve the following specifications: 

Power Supply = 1.8V



Total Current Consumption = 35dB



Cut off frequency >50MHz



AC input signal = 10mV (peak to peak)



The output is able to drive a 5pF and a 5kΩ resistive load.

3.0

DESIGN OF MULTI-STAGE MOS OPERATIONAL AMPLIFIER

Figure 1: Multistage MOS Operational Amplifier 4

Figure 1 shows the designed multistage MOS operational amplifier which is an addition of three different stages which is the common source stage, common drain stage and differential pair stage. The tsmc018n NMOS transistor model is used in order to complete this simulation. 3.1

Calculation

As mentioned in the question, the minimum gain that should be acquired is more than 35dB. The gain can be accomplished by multiplying all the gains at the specific stages which is the differential pair, common source and common drain stage. Each gain calculation is derived and shown in the upcoming sections. Differential Pair

Figure 2: Differential Pair Stage The differential pair consists of two NMOS amplifiers and a current mirror circuit and is used to aid in noise reduction and removal. The design of a differential pair stage includes four NMOS transistors and three resistors. As shown in Figure 2, MOSFET’s M1, M2, M7 & M8 is used as a transistor with the model tsmc018n. The resistors R1, R2 & R9 is also used to design the differential pair stage. Generally, MOSFET amplifiers have high sensitivity towards noise and two resistors with the value of 27kΩ is placed as a load function whereby the independent current source is replaced by a current mirror circuit with transistors M7 & M8. Though it is complicating 5

to combine a differential amplifier and current mirror circuit together, the output current can be maintained to a constant value regardless. The output voltage and input voltages act as a stage to operate the common source stage. The gain of this stage can be calculated as,

𝑉𝑜𝑢𝑡 𝑉𝑖𝑛

With assuming the values of Vdd , R D and ID , the calculations can be shown as below:

= −𝑔𝑚 𝑅𝐷 .

Load Resistance, R D = 2kΩ Drain Current, ID =

Iss 2

The equation that is conveyed when the NMOS transistor is at saturation region is shown: VD = Vdd − RD ∙ ID VD = 1.8V − (2kΩ ∙ VD = 1.8V − (2kΩ ∙ VD = 0.8V

Iss ) 2

1mA ) 2

For the 1st stage, the saturation region is expressed as: VDS ≥ VGS − VTH

VD1 − VS ≥ VG1 − Vs − VTH

Since VD1 = 0.8V, VS = 0.058V, VG = 0.6V & VTH = 0.369V

∴ 0.8V − 0.058V ≥ 0.6V − 0.058V − 0.369V 𝟎. 𝟖𝐕 ≥ 𝟎. 𝟏𝟕𝟑𝐕

Common Drain Stage The circuit for the common drain stage in the LTSpice simulation is as shown in Figure 3. The gain of the common drain stage is

𝑉𝑜𝑢𝑡 𝑉𝑖𝑛

= −𝑔𝑚 𝑅𝐷 .

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Figure 3: Common Drain Stage As shown in Figure 3, the transistor with the model tsmc018n will have the same voltage value as Vdd as there is no resistors present at the drain of the transistor. This transistor will have a load of

5kΩ and 5pF which will be connected in parallel. In this case, the voltage value across the

resistance R4=20kΩ will not be the same. The saturation region of this stage can be expressed as shown:

VDS ≥ VGS − VTH

VD4 − VS ≥ VG4 − Vs − VTH

Since VD4 = Vdd = 1.8V, VG4 = 1.09V & VTH = 0.369V

∴ 1.8V ≥ 1.09V − 0.369V 𝟏. 𝟖𝐕 ≥ 𝟎. 𝟕𝟐𝟏𝐕

Common Source Stage The common source stage of the MOS design in shown in Figure 4. The common source stage aids in amplifying the voltage gain in a system as the input that goes through the gate of the

transistor, leaves the transistor through the drain. Vm3 is where the input voltage is determined with

respect to R3=20kΩ in the circuit. The saturation region of the common source stage is also

expressed below.

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Figure 4: Common Source Stage VDS ≥ VGS − VTH

VD3 − VS ≥ VG3 − Vs − VTH

Since VD3 = 1.09V, VG3 = 0.61V, VS = 0V & VTH = 0.369V

∴ 1.09V − 0𝑉 ≥ 0.61V − 0V − 0.369V 𝟏. 𝟎𝟗𝐕 ≥ 𝟎. 𝟐𝟒𝟏𝐕

To identify the value of ID , the equation below is used where VGS = Vin2 , 1 W ID = μN COX (VGS − VTH )2 2 L

1 W ID = μN COX (Vin2 − VTH )2 2 L 𝐈𝐃 = 𝟎. 𝟏𝟑𝟔𝐦𝐀

Hence, the value of Vout2 can be calculated as shown:

Vout2 = Vdd − R D ∙ ID Vout2 = 0.453𝑉

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When the transistor is in saturation mode: Vout2 ≥ Vin2 − VTH ∴ 0.453𝑉 ≥ 0.6𝑉 − 0.369V 𝟎. 𝟒𝟓𝟑𝑽 ≥ 𝟎. 𝟐𝟑𝟏𝐕

4.0

SIMULATION RESULTS

DC Analysis

Figure 5: DC Sweep of the Differential Amplifier By conducting the DC analysis to the amplifier, the DC voltage and current and be identified to ensure that the output current is kept below 1mA. Figure 5 shows the DC sweep of the voltage value from 𝑉𝑜𝑢𝑡1 to 𝑉𝑜𝑢𝑡2 and 𝑉𝑚1 to 𝑉𝑚2 . The graph shows that the voltage value of 𝑉𝑜𝑢𝑡 and

𝑉𝑚 until it reaches an intersecting point and increases and decreases respectively to a certain point where it remains constant. Figure 6 on the other hand presents the exact characteristics where the voltage value decreases from somewhere around 1.78V till 0V. The voltage value of 𝑉𝑚1 reduces

to 0V when the value of 𝑉𝑚7 reaches 1.0V.

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Figure 6: DC Sweep of the Common Source Stage AC Analysis

Figure 7: Gain for the differential pair stage Figure 7 and 8 shows the gain achieved in both the 1st and 2nd stages which are 23.1dB and 40.5dB respectively. The bandwidth for all the gains achieved were more than 50MHz. Based on the objective of this lab, the overall gain that needs to be achieved is more than 35dB with a cutoff frequency of more than 50MHz. The desired output was achieved with the gain of 38.67dB having its cutoff frequency at 51.24MHz as shown in Figure 9. 10

Figure 8: Gain for the common source stage

Figure 9: Overall gain

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Figure 10: Input transient response Figure 10 shows the input transient response as a sine wave where the maximum voltage value which is the dc offset is 605mV. The peak to peak voltage of the input transient response is 10mV. Figure 11 on the other hand shows the output transient response whereby the maximum and minimum output obtained was 800mV and 38mV respectively.

Figure 11: Output transient response Through the values obtained in the transient response, the overall gain can be calculated using the formula as shown below: A𝑣 = 20 log (

Vout(peak to peak) ) Vin(peak to peak)

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762mV A𝑣 = 20 log ( 10mV ) A𝑣 = 𝟑𝟕. 𝟔𝟑𝐝𝐁

The gain achieved through calculations was 37.63dB whereas the gain achieved through simulation was 38.67dB. This difference of 1dB to the gain could be due to the rounded up values at the transient response which was used in the calculations. The percentage tolerance gain obtained was 2.69% which was achieved through the calculations as shown: Percentage difference =

Simulated value − Calculated value × 100 Simulated value

Percentage difference =

38.67dB − 37.63dB × 100 38.67dB

Percentage difference = 2.69%

The output current obtained through the simulation is 0.5mA which meets the requirement of having an output current less than 1mA as shown in Figure 12.

Figure 12: DC Operating point values

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5.0

DISCUSSION The MOS multistage amplifier should be designed under a few considerations. Each

transistor implemented in the amplifier has its specific characteristics whereby the DC sweep operation is used to identify the input voltages of each MOSFET to ensure that it falls in the saturation region. Initially, the DC sweep of the common drain stage was identified. The voltage value when the transistor would work is from 0.6V onwards, hence the output from the common source stage should be more than 0.6V. Later on, the DC sweep for the 2nd stage was identified where the cursor was set to 0.6V and the output voltage value from the differential pair has to be lesser than 0.64V. The differential pair stage was designed as the resistance of this stage was set to 27kΩ as the drain current obtained in one side of the current mirror was 0.136mA. Since the transistor in M7 was designed being 2 times larger than M8, the current should also be two times larger is 0.88µA. The gate voltage value at the current mirror is 0.77V. The DC sweep for the stage 1 was done whereby the intersection point identified was 0.6V which makes the stage 3 work as it has an output of 0.64V. When the input of the stage 1 is 0.6V the output identified through the DC sweep is approximately 1V. The DC sweep of the outputs which were done earlier to be compared as the output value obtained at the common drain stage was 0.3mV and 0.4mV which has a low difference. The transient response obtained from the differential pair stage has a maximum and minimum peak value of 0.67V and 0.53V respectively. On the other hand, for the common source stage, the maximum and minimum value obtained was 1.5V and 0.5V respectively which makes the common drain stage to never fall in the cutoff region. The transient value at the common drain stage shows a maximum and minimum value of 0.8V and 0.036V respectively which is somewhat closer to the definite result obtained. The gain of the differential pair stage that was obtained in the simulation section was gain of 23.1dB with a bandwidth of 311MHz and the gain of the second stage is 40.5 dB with a bandwidth of 310MHz. Even if the 1st and 2nd stage improves the voltage gain of the circuit, a high current consumption is required whereby assumptions are done multiple times by replacing each value to obtain the desired output. The resistance in the 2nd stage was assumed at 20kΩ as it has to be large to increase the voltage gain and the common drain stage aids in doing so.

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6.0

CONCLUSION To conclude about this report, the multistage operational amplifier with the specific

characteristics has been designed and analyzed. All the required objectives were successfully achieved using the LTSpice simulation software. The differential pair, common source and common drain stages were used in this op-amp whereby the 1st stage is used to reduce the noise in the system, 2nd stage is used to amplify the input signal and the 3rd stage is used as a source follower. Even though all the objectives were met, this system can be further improved by adding a PMOS transistor to the system and also by improving the input signal from the common source stage. Furthermore, the current drawn should always be in a low value which is opposed by the gain in a sense that if the gain increases, the current drawn is increased. In this case, the power consumption of the system has to be identified before designing an op-amp. Hence, this lab is completed with achieving an overall gain of 38.67dB with a cutoff frequency of 51.24MHz. The peak to peak value was also kept to 10mV while conducting this lab. All the objectives were understood well.

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